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ISL85012 Datasheet(PDF) 12 Page - Renesas Technology Corp

Part No. ISL85012
Description  12A, 3.8V to 18V Input, Synchronous Buck Regulator
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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ISL85012 Datasheet(HTML) 12 Page - Renesas Technology Corp

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ISL85012
FN8677 Rev.2.00
Page 12 of 19
Mar 17, 2017
The PWM operation is initialized by the clock from the oscillator.
The high-side MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp-up. When the
sum of the current amplifier CSA, and the slope compensation
(780mV/tSS) reaches the control reference of the current loop
(COMP), the PWM comparator sends a signal to the PWM logic to
turn off the upper MOSFET and turn on the lower MOSFET. The
lower MOSFET stays on until the end of the PWM cycle. Figure 30
shows the typical operating waveforms during Continuous
Conduction Mode (CCM) operation. The dotted lines illustrate
the sum of the compensation ramp and the current-sense
amplifier’s output.
Light-Load Operation
The ISL85012 monitor both the current in the low-side MOSFET
and the voltage of the FB node for regulation. Pulling the SYNC
pin low allows the regulator to enter discontinuous operation
when lightly loaded by operating the low-side MOSFET in Diode
Emulation Mode (DEM). In this mode, reverse current is not
allowed in the inductor and the output falls naturally to the
regulation voltage before the high-side MOSFET is switched for
the next cycle. In CCM mode, the boundary is set by Equation 1:
where D = duty cycle, fSW = switching frequency, L = inductor
value, IOUT = output loading current, and VOUT = output voltage.
Table 3 shows the operating modes determined by the SYNC pin.
Synchronization
The ISL85012 can be synchronized from 100kHz to 1MHz by an
external signal applied to the SYNC pin. The rising edge on the SYNC
triggers the rising edge of the PHASE pulse. Make sure the on-time
of the SYNC pulse is longer than 100ns.
Output Voltage Selection
The regulator output voltages can be programmed using external
resistor dividers that scale the voltage feedback relative to the
internal reference voltage. The scaled voltage is fed back to the
inverting input of the error amplifier; refer to Figure 31.
The output voltage programming resistor, R2, will depend on the
value chosen for the feedback resistor, R1, and the desired
output voltage, VOUT; see Equation 2. The R1 value will
determine the gain of the feedback loop. See “Loop
Compensation Design” on page 15 for more details. The value for
the feedback resistor is typically between 1kΩ and 370kΩ.
If the desired output voltage is 0.6V, then R2 is left unpopulated.
R1 is still required to set the low frequency pole of the modulator
compensation.
Protection Features
The regulator limits current in all on-chip power devices.
Overcurrent limits are applied to the two output switching
MOSFETs as well as to the LDO linear regulator that feeds VDD.
The output overvoltage protection circuitry on the switching
regulator provides a second layer of protection.
High-Side MOSFET Overcurrent Protection
Current flowing through the internal high-side switching MOSFET
is monitored during on-time. The current, which is temperature
compensated, will compare to a default 18A overcurrent limit.
The ISL85012 offers two OCP schemes to implement the on-time
overcurrent protection, which can be configured by the MODE pin
(see Table 4).
If the measured current exceeds the overcurrent limit, the high-side
MOSFET is immediately turned off and will not turn on again until
the next switching cycle. After eight consecutive cycles of overcurrent
events detected, the converter will operate at the selected OCP
scheme according to the MODE pin configuration. A cycle where an
overcurrent condition is not detected will reset the counter.
The switching frequency will be folded back if the OCP is tripped
and the on-time of the PWM is less than 250ns to lower down the
average inductor current.
FIGURE 30. PWM OPERATION WAVEFORMS
TABLE 3. OPERATION MODE SETTING
SYNC
Float
GND
Force CCM
DEM
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
IOUT
VOUT 1D

2LfSW
-----------------------------------
=
(EQ. 1)
FIGURE 31. EXTERNAL RESISTOR DIVIDER
TABLE 4. OCP SCHEME SETTING
MODE
Float
GND
Enter hiccup mode after eight
consecutive cycle-by-cycle limit.
Blanking time is 150ms
Enter latch-off mode after
eight consecutive cycle-by-cycle
limit
R2
R1 0.6V
VOUT 0.6V
----------------------------------
=
(EQ. 2)
R1
R2
0.6V
EA
REFERENCE
VOUT


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