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ISL85012 Datasheet(PDF) 4 Page - Renesas Technology Corp

Part No. ISL85012
Description  12A, 3.8V to 18V Input, Synchronous Buck Regulator
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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ISL85012 Datasheet(HTML) 4 Page - Renesas Technology Corp

 
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ISL85012
FN8677 Rev.2.00
Page 4 of 19
Mar 17, 2017
Pin Configuration
ISL85012
(15 LD 3.5mmx3.5mm TQFN)
TOP VIEW
FB
PVIN
PHASE
GND
COMP
EN
PG
DNC
DNC
BOOT
VDD
FREQ
SYNC
12
3
4
5
6
7
8
10
9
11
12
13
14
15
MODE
VIN
PVIN
9
PHASE
8
GND
7
Pin Descriptions
PIN#
PIN
NAME
DESCRIPTION
1
SYNC
Synchronization and mode selection pin. Connect to VDD or float for PWM mode. Connect to GND for DCM mode in the light-load
condition. Connect to an external clock signal for synchronization with the rising edge trigger.
2
MODE
OCP scheme select pin. Short it to GND for latch-off mode. Float it for hiccup mode.
3
FREQ
Default frequency selection pin. Short it to GND for 300kHz. Float it for 600kHz.
4
PG
Power-good, open-drain output. It requires a pull-up resistor (10kΩ to 100kΩ) between PG and VDD or a voltage not exceeding
5.5V. PG pulls high when FB is in the range of ~90% to ~116% of its intended value.
5
VDD
Low dropout linear regulator decoupling pin. The VDD is the internally generated 5V supply voltage and is derived from VIN. The
VDD is used to power all the internal core analog control blocks and drivers. Connect a 2.2µF capacitor from VDD to the board
ground plane. If the VIN is between 3V to 5.5V, then connect VDD directly to VIN to improve efficiency.
6
BOOT
BOOT is the floating bootstrap supply pin for the high-side power MOSFET gate driver. A bootstrap capacitor, usually 0.1µF, is
required from BOOT to PHASE.
7
GND
Reference of the power circuit. For thermal relief, this pin should be connected to the ground plane by vias.
8
PHASE Switch node connection to the internal power MOSFETs (source of upper FET and drain of lower FET) and the external output
inductor.
9
PVIN
Input supply for the PWM regulator power stage. A decoupling capacitor, typically ceramic, is required to be connected between
this pin and GND.
10
FB
Inverting input to the voltage loop error amplifier. The output voltage is set by an external resistor divider connected to FB.
11
COMP
Output of the error amplifier. Compensation network between COMP and FB to configure external compensation. Place a 200Ω
resistor between COMP and GND for internal compensation, which is used to meet most applications.
12, 13
DNC
Do Not Connect to pin. Float the pins in the design.
14
EN
Enable input. The regulator is held off when this pin is pulled to ground. The device is enabled when the voltage on this pin rises
to about 0.6V.
15
VIN
Input supply for the control circuit and the source for the internal linear regulator that provides bias for the IC.
A decoupling capacitor, typically 1µF ceramic, is required connected between VIN and GND.


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