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ISL62771 Datasheet(PDF) 32 Page - Renesas Technology Corp

Part No. ISL62771
Description  Multiphase PWM Regulator for AMD Fusion™ Mobile CPUs Using SVI 2.0
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL62771 Datasheet(HTML) 32 Page - Renesas Technology Corp

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ISL62771
FN8321 Rev 4.00
Page 32 of 35
November 18, 2015
14
ISUMP
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals
traces in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the
traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the
pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor.
The following drawings show the two preferred ways of routing current sensing traces.
15
ISUMN
16
VSEN
Place the filter on these pins in close proximity to the controller for good coupling.
17
RTN
18
FB
Place the compensation components in general proximity of the controller.
19
COMP
20
PGOOD
No special consideration.
21
BOOT1
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
22
UGATE1
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE1 to the Core VR
Channel 1 high-side MOSFET source pin instead of a general connection to PHASE1 copper is recommended for
better performance.
23
PHASE1
24
LGATE1
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
25
VDD
A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor
in close proximity to the pin with the filter resistor nearby the IC.
26
VDDP
A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor
in close proximity to the pin.
27
LGATE2
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
28
PHASE2
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE2 to the Core VR
Channel 2 high-side MOSFET source pin instead of a general connection to PHASE2 copper is recommended for
better performance.
29
UGATE2
30
BOOT2
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
31
BOOT_NB
32
UGATE_NB
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE_NB to the
Northbridge VR high-side MOSFET source pin instead of a general connection to PHASE_NB copper is
recommended for better performance.
33
PHASE_NB
34
LGATE_NB
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
35
PGOOD_NB
No special consideration.
TABLE 13. LAYOUT CONSIDERATIONS FOR THE ISL62771 CONTROLLER (Continued)
ISL62771 PIN
SYMBOL
LAYOUT GUIDELINES
INDUCTOR
CURRENT-SENSING TRACES
VIAS
INDUCTOR
CURRENT-SENSING TRACES


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