NCD5700

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3

Table 1. PIN FUNCTION DESCRIPTION

Pin Name

No.

I/O/x

Description

EN

1

I

Enable input allows additional gating of VOH and VOL, and can be used when the driver output

needs to be turned off independent of the Microcontroller input.

VIN

2

I

Input signal to control the output. In applications which require galvanic isolation, VIN is generated

at the opto output, the pulse transformer secondary or the digital isolator output. There is a signal

inversion from VIN to VOH/VOL. VIN is internally clamped to 5.5 V and has a pull−up resistor of

1M

W to ensure that output is low in the absence of an input signal. A minimum pulse−width is re-

quired at VIN before VOH/VOL are activated.

VREF

3

O

5 V Reference generated within the driver is brought out to this pin for external bypassing and for

powering low bias circuits (such as digital isolators).

FLT

4

O

Fault output (active low) that allows communication to the main controller that the driver has en-

countered a fault condition and has deactivated the output. Truth Table is provided in the datasheet

to indicate conditions under which this signal is asserted. Capable of driving optos or digital isolators

when isolation is required.

GNDA

5

x

This pin provides a convenient connection point for bypass capacitors (e.g REF) on the left side of

the package.

NC

6,8

x

Pins not internally connected.

RSVD

7

x

Reserved. No connection is allowed.

DESAT

9

I

Input for detecting the desaturation of IGBT due to a fault condition. A capacitor connected to this

pin allows a programmable blanking delay every ON cycle before DESAT fault is processed, thus

preventing false triggering.

VCC

10

x

Positive bias supply for the driver. The operating range for this pin is from UVLO to the maximum. A

good quality bypassing capacitor is required from this pin to GND and should be placed close to the

pins for best results.

VOH

11

O

Driver high output that provides the appropriate drive voltage and source current to the IGBT gate.

VOL

12

O

Driver low output that provides the appropriate drive voltage and sink current to the IGBT gate. VOL

is actively pulled low during start−up and under Fault conditions.

GND

13

x

This pin should connect to the IGBT Emitter with a short trace. All power pin bypass capacitors

should be referenced to this pin and kept at a short distance from the pin.

VEE

14

x

A negative voltage with respect to GND can be applied to this pin and that will allow VOL to go to a

negative voltage during OFF state. A good quality bypassing capacitor is needed from VEE to GND.

If a negative voltage is not applied or available, this pin must be connected to GND.

VEEA

15

x

Analog version of the VEE pin for any signal trace connection. VEE and VEEA are internally con-

nected.

CLAMP

16

I/O

Provides clamping for the IGBT gate during the off period to protect it from parasitic turn−on. To be

tied directly to IGBT gate with minimum trace length for best results.