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ISL6336B Datasheet(PDF) 18 Page - Renesas Technology Corp

Part No. ISL6336B
Description  6-Phase PWM Controller with Light Load Efficiency Enhancement and Current Monitoring
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL6336B Datasheet(HTML) 18 Page - Renesas Technology Corp

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ISL6336B
FN6696 Rev 3.00
Page 18 of 32
May 5, 2016
Load-Line Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of the output
voltage on the load current is often termed “droop” or “load
line” regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a direction
which works to achieve the load-line regulation required by
these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from the fast changes of the load-current demand.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 6, a current proportional to the average
current of all active channels, IAVG, flows from FB through a
load-line regulation resistor RFB. The resulting voltage drop
across RFB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined in Equation 8.
The regulated output voltage is reduced by the droop voltage
VDROOP. The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
Where VREF is the reference voltage, VOFS is the
programmed offset voltage, IOUT is the total output current
of the converter, RISEN is the sense resistor connected to
the ISEN+ pin, and RFB is the feedback resistor, N is the
active channel number, and RX is the DCR, or RSENSE
depending on the sensing method.
Therefore the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 10:
Output-Voltage Offset Programming
The ISL6336B allows the designer to accurately adjust the
offset voltage. When resistor, ROFS, is connected between
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (IOFS) to flow into OFS. If
ROFS is connected to ground, the voltage across it is
regulated to 0.4V, and IOFS flows out of OFS. A resistor
between DAC and REF, RREF, is selected so that the
product (IOFS x ROFS) is equal to the desired offset voltage.
These functions are shown in Figure 7.
Once the desired output offset voltage has been determined,
use Equations 11 and 12 to set ROFS:
For Positive Offset (connect ROFS to VCC):
For Negative Offset (connect ROFS to GND):
1
001111
1
0.61875
1
010000
0
0.61250
1
010000
1
0.60625
1
010001
0
0.60000
1
010001
1
0.59375
1
010010
0
0.58750
1
010010
1
0.58125
1
010011
0
0.57500
1
010011
1
0.56875
1
010100
0
0.56250
1
010100
1
0.55625
1
010101
0
0.55000
1
010101
1
0.54375
1
010110
0
0.53750
1
010110
1
0.53125
1
010111
0
0.52500
1
010111
1
0.51875
1
011000
0
0.51250
1
011000
1
0.50625
1
011001
0
0.50000
1
111111
0
OFF
1
111111
1
OFF
TABLE 3. VR11 VID 8-BIT (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
VDROOP
IAVG RFB
=
(EQ. 8)
VOUT
VREF VOFS
IOUT
N
-------------
RX
RISEN
------------------ RFB




=
(EQ. 9)
RLL
RFB
N
------------
RX
RISEN
------------------
=
(EQ. 10)
ROFS
1.6 RREF
VOFFSET
----------------------------
=
(EQ. 11)
ROFS
0.4 RREF
VOFFSET
----------------------------
=
(EQ. 12)


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