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IDT72T7285L5BBI Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT72T7285L5BBI Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 53 page  4 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 DESCRIPTION (CONTINUED) The device can be configured with different input and output bus widths as shown in Table 1. A Big-Endian/Little-Endian data word format is provided. This function is usefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andread out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected, then the most significant byte (word) of the long word written into the FIFO will bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired is configured during master reset by the state of the Big-Endian ( BE)pin.See Figure 5 for Bus-Matching Byte Arrangement. The Interspersed/Non-Interspersed Parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If Interspersed Parity mode is selected, then the FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and D35 during the parallel programming of the flag offsets. If Non-Interspersed Paritymodeisselected,thenD8andD17areassumedtobevalidbits. IPmode is selected during Master Reset by the state of the IP input pin. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol inputs) will immediately take the device out of the power down state. Both an Asynchronous Output Enable pin ( OE) and Synchronous Read Chip Select pin ( RCS)areprovidedontheFIFO.TheSynchronousReadChip SelectissynchronizedtotheRCLK.Boththeoutputenableandreadchipselect control the output buffer of the FIFO, causing the buffer to be either HIGH impedance or LOW impedance. A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and Boundary Scan Architecture. The TeraSync FIFO has the capability of operating its ports (write and/or read) in either LVTTL or HSTL mode, each ports selection independent of the other. The write port selection is made via WHSTL and the read port selection via RHSTL. An additional input SHSTL is also provided, this allows the user to select HSTL operation for other pins on the device (not associated with the write or read ports). The IDT72T7285/72T7295/72T72105/72T72115 are fabricated using IDT’s high speed submicron CMOS technology. |
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