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RX5500 Datasheet(PDF) 6 Page - Murata Manufacturing Co., Ltd.

Part No. RX5500
Description  RFM products are now Murata products
Download  9 Pages
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Maker  MURATA [Murata Manufacturing Co., Ltd.]
Homepage  http://www.murata.com
Logo MURATA - Murata Manufacturing Co., Ltd.

RX5500 Datasheet(HTML) 6 Page - Murata Manufacturing Co., Ltd.

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©2010-2015 by Murata Electronics N.A., Inc.
RX5500 (R) 4/15/15
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slicing level from 0 to 90 mV, and is set with a resistor between the
RREF and THLD1 pins. This threshold allows a trade-off between
receiver sensitivity and output noise density in the no-signal
condition. For best sensitivity, the threshold is set to 0. In this case,
noise is output continuously when no signal is present. This, in
turn, requires the circuit being driven by the RXDATA pin to be able
to process noise (and signals) continuously.
This can be a problem if RXDATA is driving a circuit that must
“sleep” when data is not present to conserve power, or when it its
necessary to minimize false interrupts to a multitasking processor.
In this case, noise can be greatly reduced by increasing the
threshold level, but at the expense of sensitivity. The best 3 dB
bandwidth for the low-pass filter is also affected by the threshold
level setting of DS1. The bandwidth must be increased as the
threshold is increased to minimize data pulse-width variations with
signal amplitude.
Receiver Pulse Generator and RF Amplifier Bias
The receiver amplifier-sequence operation is controlled by the
Pulse Generator & RF Amplifier Bias module, which in turn is
controlled by the PRATE and PWIDTH input pins, and the Power
Down (sleep) Control Signal from the Bias Control function.
In the low data rate mode, the interval between the falling edge of
one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse
tPRI is set by a resistor between the PRATE pin and ground. The
interval can be adjusted between 0.1 and 5 µs. In the high data rate
mode (selected at the PWIDTH pin) the receiver RF amplifiers
operate at a nominal 50%-50% duty cycle. In this case, the start-
to-start period tPRC for ON pulses to RFA1 are controlled by the
PRATE resistor over a range of 0.1 to 1.1 µs.
In the low data rate mode, the PWIDTH pin sets the width of the
ON pulse tPW1 to RFA1 with a resistor to ground (the ON pulse
width tPW2 to RFA2 is set at 1.1 times the pulse width to RFA1 in
the low data rate mode). The ON pulse width tPW1 can be adjusted
between 0.55 and 1 µs. However, when the PWIDTH pin is
connected to Vcc through a 1 M resistor, the RF amplifiers operate
at a nominal 50%-50% duty cycle, facilitating high data rate
operation. In this case, the RF amplifiers are controlled by the
PRATE resistor as described above.
Both receiver RF amplifiers are turned off by the Power Down
Control Signal, which is invoked in the sleep mode.
Receiver Mode Control
The receiver operating modes – receive and power-down (sleep),
are controlled by the Bias Control function, and are selected with
the CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and
CNTRL0 both high place the unit in the receive mode. Setting
CNTRL1 and CNTRL0 both low place the unit in the power-down
(sleep) mode. CNTRL1 and CNTRL0 are CMOS compatible
inputs. These inputs must be held at a logic level; they cannot be
left unconnected.
Receiver Event Timing
Receiver event timing is summarized in Table 1. Please refer to
this table for the following discussions.
Turn-On Timing
The maximum time tPR required for the receive function to become
operational at turn on is influenced by two factors. All receiver
circuitry will be operational 5 ms after the supply voltage reaches
2.2 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC
stabilized in 3 time constants
(3*tBBC). The total turn-on time to
stable receiver operation for a 10 ms power supply rise time is:
tPR = 15 ms + 3*tBBC
Sleep and Wake-Up Timing
The maximum transition time from the receive mode to the power-
down (sleep) mode tRS is 10 µs after CNTRL1 and CNTRL0 are
both low (1 µs fall time).
The maximum transition time tSR from the sleep mode to the
receive mode is 3*tBBC, where tBBC is the BBOUT-CMPIN
coupling-capacitor time constant. When the operating temperature
is limited to 60 °C, the time required to switch from sleep to receive
is dramatically less for short sleep times, as less charge leaks
away from the BBOUT- CMPIN coupling capacitor.
Pulse Generator Timing
In the low data rate mode, the interval tPRI between the falling edge
of an ON pulse to the first RF amplifier and the rising edge of the
next ON pulse to the first RF amplifier is set by a resistor RPR
between the PRATE pin and ground. The interval can be adjusted
between 0.1 and 5 µs with a resistor in the range of 51 K to 2000
K. The value of the RPR is given by:
RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms
In the high data rate mode (selected at the PWIDTH pin) the
receiver RF amplifiers operate at a nominal 50%-50% duty cycle.
In this case, the period tPRC from the start of an ON pulse to the
first RF amplifier to the start of the next ON pulse to the first RF
amplifier is controlled by the PRATE resistor over a range of 0.1 to
1.1 µs using a resistor of 11 K to 220 K. In this case RPR is given
by:
RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms
In the low data rate mode, the PWIDTH pin sets the width of the
ON pulse to the first RF amplifier tPW1 with a resistor RPW to
ground (the ON pulse width to the second RF amplifier tPW2 is set
at 1.1 times the pulse width to the first RF amplifier in the low data
rate mode). The ON pulse width tPW1 can be adjusted between
0.55 and 1 µs with a resistor value in the range of 200 K to 390 K.
The value of RPW is given by:
RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms
However, when the PWIDTH pin is connected to Vcc through a 1
M resistor, the RF amplifiers operate at a nominal 50%-50% duty
cycle, facilitating high data rate operation. In this case, the RF
amplifiers are controlled by the PRATE resistor as described
above.
LPF Group Delay
The low-pass filter group delay is a function of the filter 3 dB
bandwidth, which is set by a resistor RLPF to ground at the LPFADJ
pin. The minimum 3 dB bandwidth fLPF = 1445/RLPF, where fLPF is
in kHz, and RLPF is in kilohms.
The maximum group delay tFGD = 1750/fLPF = 1.21*RLPF, where
tFGD is in µs, fLPF in kHz, and RLPF in kilohms.


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