6

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync

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 72-BIT FIFO

16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

PIN DESCRIPTION

Symbol

Name

I/O TYPE

Description

LVTTL

A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW

Read Port

INPUT

willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.

LVTTL

A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW

WritePort

INPUT

will select Asynchronous operation.

Big-Endian/

LVTTL

During Master Reset, a LOW on

BE will select Big-Endian operation. A HIGH on BE during Master Reset

Little-Endian

INPUT

willselectLittle-Endianformat.

Bus-Matching

LVTTL

BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size

INPUT

configuration.

HSTL-LVTTL Data inputs for a 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused input pins are in a don’t care

INPUT

state.

EF/OR

Empty Flag/

HSTL-LVTTL In the IDT Standard mode, the

EFfunctionisselected.EFindicateswhetherornottheFIFOmemoryisempty.

Output Ready

OUTPUT

In FWFT mode, the

OR function is selected. OR indicates whether or not there is valid data available at the

outputs.

ERCLK RCLK Echo

HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.

OUTPUT

EREN

Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.

OUTPUT

FF/IR

Full Flag/

HSTL-LVTTL In the IDT Standard mode, the

FF function is selected. FF indicates whether or not the FIFO memory is

Input Ready

OUTPUT

full. In the FWFT mode, the

IR function is selected. IR indicates whether or not there is space available for

writing to the FIFO memory.

LVTTL

During Master Reset, this input along with FSEL1 and the

LD pin, will select the default offset values for the

INPUT

programmable flags

PAE and PAF. There are up to eight possible settings available.

LVTTL

During Master Reset, this input along with FSEL0 and the

LD pin will select the default offset values for the

INPUT

programmable flags

PAE and PAF. There are up to eight possible settings available.

FWFT/

First Word Fall

HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin

SI

Through/Serial In

INPUT

functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been

selected then the FIFO must be set-up in IDT Standard mode.

HF

Half-Full Flag

HSTL-LVTTL

HF indicates whether the FIFO memory is more or less than half-full.

OUTPUT

Interspersed Parity

LVTTL

During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed

INPUT

Parity mode.

InputWidth

LVTTL

This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration.

INPUT

LD

Load

HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the

LD input along with FSEL0 and FSEL1,

INPUT

determines one of eight default offset values for the

PAEandPAFflags,alongwiththemethodbywhichthese

offsetregisterscanbeprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswriting

to and reading from the offset registers. THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE OR

READ DATA TO/FROM THE FIFO MEMORY.

MARK

Mark for Retransmit HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit

INPUT

operation will reset the read pointer to this position.

MRS

Master Reset

HSTL-LVTTL

MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master

INPUT

Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,

Synchronous/Asynchronousoperationofthereadorwriteport,oneofeightprogrammableflagdefaultsettings,

serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatencytimingmode,

interspersed parity, and synchronous versus asynchronous programmable flag timing modes.

OE

OutputEnable

HSTL-LVTTL

INPUT

OE input is the only input that provide High-Impedance control of the data outputs.

OutputWidth

LVTTL

This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.

INPUT