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DS3065W Datasheet(PDF) 4 Page - Maxim Integrated Products

Part No. DS3065W
Description  3.3V Single-Piece 8Mb Nonvolatile SRAM with Clock
Download  18 Pages
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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DS3065W Datasheet(HTML) 4 Page - Maxim Integrated Products

 
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3.3V Single-Piece 8Mb Nonvolatile SRAM
with Clock
4
_____________________________________________________________________
Note 1:
IRQ/FT and RST are open-drain outputs and cannot source current. External pullup resistors should be connected to these
pins to realize a logic-high level.
Note 2:
These parameters are sampled with a 5pF load and are not 100% tested.
Note 3:
tWP is specified as the logical AND of CE with WE for SRAM writes, or CS with WE for RTC writes. tWP is measured from
the latter of the two related edges going low to the earlier of the two related edges going high.
Note 4:
tWR1 and tDH1 are measured from WE going high.
Note 5:
tWR2 and tDH2 are measured from CE going high for SRAM writes or CS going high for RTC writes.
Note 6:
tDS is measured from the earlier of CE or WE going high for SRAM writes, or from the earlier of CS or WE going high for
RTC writes.
Note 7:
In a power-down condition, the voltage on any pin may not exceed the voltage on VCC.
Note 8:
The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the
user. Minimum expected data-retention time is based upon a maximum of two +230°C convection reflow exposures, fol-
lowed by a fully charged cell. Full charge occurs with the initial application of VCC for a minimum of 96 hours. This parame-
ter is assured by component selection, process control, and design. It is not measured directly during production testing.
Note 9:
WE is high for any read cycle.
Note 10: OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
Note 11: If the CE or CS low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a
high-impedance state during this period.
Note 12: If the CE or CS high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a
high-impedance state during this period.
Note 13: If WE is low or the WE low transition occurs prior to or simultaneously with the related CE or CS low transition, the output
buffers remain in a high-impedance state during this period.
DATA RETENTION
(TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Expected Data-Retention Time
(Per Charge)
tDR
(Notes 7, 8)
2
3
years


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