PRELIMINARY
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
Document #: 38-05503 Rev. *A
Page 7 of 21
Application Example[1]
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
DQ
DQ
Write Cycle:
Load address; wait one cycle; input write data on
consecutive K and K rising edges.
L-H
L
L
D(A + 0)at K(t + 1)
↑
D(A + 1) at K(t + 1)
↑
Read Cycle:
Load address; wait one and a half cycle; read data
on consecutive C and C rising edges.
L-H
L
H
Q(A + 0) at C(t + 1)
↑
Q(A + 1) at C(t + 2)
↑
NOP: No Operation
L-H
H
X
High-Z
High-Z
Standby: Clock Stopped
Stopped
X
X
Previous State
Previous State
Write Cycle Descriptions (CY7C1392AV18 and CY7C1393AV18) [2, 8]
BWS0 BWS1
KK
Comments
L
L
L-H
-
During the Data portion of a Write sequence
:
CY7C1392AV18
− both nibbles (D[7:0]) are written into the device,
CY7C1393AV18
− both bytes (D[17:0]) are written into the device.
L
L
-
L-H During the Data portion of a Write sequence
:
CY7C1392AV18
− both nibbles (D[7:0]) are written into the device,
CY7C1393AV18
− both bytes (D[17:0]) are written into the device.
L
H
L-H
-
During the Data portion of a Write sequence
:
CY7C1392AV18
− only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,
CY7C1393AV18
− only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.
L
H
-
L-H During the Data portion of a Write sequence
:
CY7C1392AV18
− only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,
CY7C1393AV18
− only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.
Notes:
1. The above application shows four DDR-II SIO being used.
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
↑ represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1, t + 2 and t +3 are the first, second and third clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. Assumes a Write cycle was initiated per the Write Cycle Description Truth Table. BWS0, BWS1 in the case of CY7C1392AV18 and CY7C1393AV18 and also
BWS2, BWS3 in the case of CY7C1394AV18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
LD
#
R/W
#
B
W
#
Vt = VREF
CC#
CQ
CQ#
K#
ZQ
Q
D
K
CC# K
BUS
MASTER
(CPU
or
ASIC)
SRAM 1
SRAM 4
DATA IN
DATA OUT
Address
LD#
R/W#
BWS#
SRAM 1 Input CQ
SRAM 1 Input CQ#
SRAM 4 Input CQ
SRAM 4 Input CQ#
Source K
Source K#
Delayed K
Delayed K#
R = 50
Ohms
R = 250
Ohms
CQ
CQ#
K#
ZQ
Q
LD
#
R/W
#
B
W
S
#
LD
#
R/W
#
Vt
Vt
Vt
R
R
R
A
A
D
R = 250
Ohms
B
W
S
#
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