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ADSP-21161N Datasheet(PDF) 8 Page - Analog Devices |
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ADSP-21161N Datasheet(HTML) 8 Page - Analog Devices |
8 / 60 page ADSP-21161N –8– REV. A or DMA-transferred to on-chip memory. Each link port has its own double-buffered input and output registers. Clock/acknowl- edge handshaking controls link port transfers. Transfers are programmable as either transmit or receive. Serial Ports The ADSP-21161N features four synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. Each serial port is made up of two data lines, a clock and frame sync. The data lines can be programmed to either transmit or receive. Figure 4. Shared Memory Multiprocessing System ACK OE ADDR DATA CS WE GLOBAL MEMORY AND PERIPHERALS (OPTIONAL) ADSP-21161N #1 ADDR23-0 CONTROL ADSP-21161N #3 ID2-0 RESET CLKIN 3 ADSP-21161N #4 CLOCK ADDR DATA SDRAM (OPTIONAL) CS ADDR DATA BOOT EPROM (OPTIONAL) ID2-0 RESET CLKIN CONTROL ADSP-21161N #2 ID2-0 RESET CLKIN 2 1 ADDR DATA HOST PROCESSOR INTERFACE (OPTIONAL) WE RAS CAS DQM CLK A10 CKE CS DATA47-16 SDWE RAS CAS DQM SDCLK1-0 SDA10 SDCKE BR6-2 RD MS3-0 SBTS CS ACK BR1 REDY HBG HBR WR BMS ADDR23-0 RESET DATA47-16 ADDR23-0 DATA47-16 |
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Similar Description - ADSP-21161N |
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