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ADS5121 Datasheet(PDF) 15 Page - Texas Instruments |
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ADS5121 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 17 page  ADS5121 15 SBAS281 www.ti.com DATA OUTPUT FORMAT The output data format of the ADS5121 is a positive Straight Offset Binary (SOB) code. Tables I and II show output coding of a single-ended and differential signal. For all data output channels, the MSBs are located at the D9x pins. channels. Note that the OE pin has no internal pull-up resistor and therefore requires a defined potential to be applied. The timing relations between OE and the output bus enable/disable times are shown in the Timing Diagram. POWER-DOWN (STANDBY) The ADS5121 is equipped with a power-down function for each of the eight channels. Labeled as STBY pins, the channel is in normal operating mode when the STBY pin is connected to logic high (H = 1). The selected ADC channel will be in a power-down mode if the corresponding STBY pin is connected to logic LOW (L = 0). The logic levels for the STBY pins are dependent on the DRVDD supply. The power- down function controls internal biasing nodes, and as a consequence, any data present in the pipeline of the con- verter will become invalid. This is independent of whether the clock remains applied during power-down or not. Following a power-up, new valid data will become available after a minimum of seven clock cycles. As a note, the operation of the STBY pins is not intended for the use of dynamically multiplexing between the eight channels of the ADS5121. DIGITAL OUTPUT DRIVER SUPPLY, DRVDD The ADS5121 uses a dedicated supply connection for the output logic drivers, DRVDD, along with its digital driver ground connections, labeled DRGND. Setting the voltage at DRVDD to either +3.3V or +1.8V also sets the output logic levels accordingly, allowing the ADS5121 to directly interface to a selected logic family. The output stages are designed to supply sufficient current to drive a variety of logic families. However, it is recommended to use the ADS5121 with a +1.8V driver supply. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply lines, which otherwise may affect the AC performance of the converter. In some applications it might be advantageous to decouple the DRVDD supply with additional capacitors or a pi-filter. GROUNDING AND DECOUPLING Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high- frequency designs. Multilayer pc-boards are recommended for best performance since they offer distinct advantages such as minimizing ground impedance, separation of signal layers by ground layers, etc. The ADS5121 should be treated as an analog component. Whenever possible, the supply pins should be powered by the analog supply. This will ensure the most consistent results, since digital supply lines often carry high levels of noise which otherwise would be coupled into the converter and degrade the achievable per- formance. The ground pins should directly connect to an analog ground plane covering the pc-board area under the converter. While designing the layout it is important to keep the analog signal traces separated from any digital line to prevent noise coupling onto the analog signal path. Due to its high sampling rate, the ADS5121 generates high-frequency current transients and noise (clock feedthrough) that are fed SINGLE-ENDED INPUT STRAIGHT OFFSET BINARY (AIN– = CML) (SOB) +FS – 1LSB (AIN+ = CML + FSR/2) 11 1111 1111 +1/2 FS 11 0000 0000 Bipolar Zero (AIN+ = CML) 10 0000 0000 –1/2 FS 01 0000 0000 –FS (AIN+ = CML – FSR/2) 00 0000 0000 TABLE I. Coding Table for Single-Ended Input Configuration with Input AIN– Tied to the Common-Mode Volt- age (CML). STRAIGHT OFFSET BINARY DIFFERENTIAL INPUT (SOB) +FS – 1LSB (AIN+ = REFT, AIN– = REFB) 11 1111 1111 +1/2 FS 11 0000 0000 Bipolar Zero (AIN+ = AIN– = CML) 10 0000 0000 –1/2 FS 01 0000 0000 –FS (AIN+ = REFB, AIN– = REFT) 00 0000 0000 TABLE II. Coding Table for Differential Input Configuration and 1VPP Full-Scale Range. DIGITAL OUTPUT LOADING Minimizing the capacitive loading on the digital outputs is very important in achieving the best performance. The total load capacitance is typically made up of two sources: the next stage input capacitance, and the parasitic/pc-board capacitance. It is recommended to keep the total capacitive loading on the data lines as low as possible ( ≤ 20pF). Higher capacitive loading will cause larger dynamic currents as the digital outputs are dynamic states. High current surges may cause feedback into the analog portion of the ADS5121 and affect the performance. If necessary, external buffers or latches close to the converter’s output pins may be used to minimize the capacitive loading. A suggested device is the SN74AVC16827 (20-bit buffer/driver), a member of the ‘Ad- vanced Very Low Voltage CMOS’ logic family (AVC). Using such a logic device can also provide the added benefit of isolating the ADS5121 from any digital noise activities on the bus coupling back high-frequency noise. Some applications may also benefit from the use of series resistors ( ≤ 100Ω) in the data lines. This will provide a current limit and reduce any existing over- or undershoot. OUTPUT ENABLE The ADS5121 provides one output enable pin (OE) that controls the digital outputs of all channels simultaneously. A LOW (L = 0) level on the OE pin will have all channels active and the converter in normal operation. Taking the OE pin HIGH (H = 1) will disable or tri-state the outputs of all |
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