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ADS5121 Datasheet(PDF) 4 Page - Texas Instruments

Part No. ADS5121
Description  8-Channel, 10-Bit, 40MSPS, 1.8V CMOS ANALOG-TO-DIGITAL CONVERTER
Download  17 Pages
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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ADS5121 Datasheet(HTML) 4 Page - Texas Instruments

 
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ADS5121
4
SBAS281
www.ti.com
ADS5121
AC CHARACTERISTICS
AVDD = DVDD = 1.8V, DRVDD = 3.3V, 50% Clock Duty Cycle, CLK = 40MSPS, Analog Input at –0.5dBFS Input Span, Internal Voltage Reference, IREFR = 6.8kΩ,
TMIN = –40°C, TMAX = +85°C, and typical values at TA = 25°C, unless otherwise noted.
ADS5121
SWITCHING CHARACTERISTICS
AVDD = DVDD = 1.8V, DRVDD = 3.3V, 50% Clock Duty Cycle, CLK = 40MSPS, Analog Input at –0.5dBFS Input Span, Internal Voltage Reference, TMIN = –40°C,
TMAX = +85°C, and typical values at TA = 25°C.
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Maximum Conversion Rate
5
40
MSPS
Clock Duty Cycle
DCASEL Enabled
30 to 70
%
Data Latency(1)
6.5
Clk Cycles
Clock
↓ to Data Valid
tDO(1)
810
ns
OE
↓ to Outputs Enabled
tEN(1)
8ns
OE
↑ Rising to Outputs Tri-Stated
tDIS
8ns
Aperture Delay
1ns
Aperture Uncertainty (Jitter)
2
ps, r ms
NOTE: (1) See timing diagram.
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Signal-to-Noise Ratio
(SNR)
fIN = 3.5MHz
56
60
dB
fIN = 10MHz
56
60
dB
fIN = 20MHz
60
dB
Signal-to-Noise and Distortion
(SINAD)
fIN = 3.5MHz
56
59
dB
fIN = 10MHz
56
59
dB
fIN = 20MHz
59
dB
Effective Number of Bits
(ENOB)
fIN = 3.5MHz
9.0
9.5
Bits
fIN = 10MHz
9.0
9.5
Bits
fIN = 20MHz
9.5
Bits
Spurious-Free Dynamic Range
(SFDR)
fIN = 3.5MHz
66
75
dBc
fIN = 10MHz
65
74
dBc
fIN = 20MHz
73
dBc
2nd-Harmonic Distortion
(HD2)
fIN = 3.5MHz
69
85
dBc
fIN = 10MHz
68
85
dBc
fIN = 20MHz
84
dBc
3rd-Harmonic Distortion
(HD3)
fIN = 3.5MHz
66
77
dBc
fIN = 10MHz
65
75
dBc
fIN = 20MHz
73
dBc
2-Tone Intermodulation Distortion
(IMD)
f1 = 4.43MHz, f2 = 4.53MHz at –6.5dB
–69
dBFS
Channel-to-Channel Crosstalk
fIN = 10MHz, DRVDD = 3.3V
89
dB
Effective Resolution Bandwidth
22
MHz
Over-Voltage Recovery Time(1)
20
ns
Differential Gain(1)
±1%
Differential Phase(1)
±0.25
Degrees
NOTE: (1) Assured by design.
TIMING DIAGRAM (Per ADC Channel)
Analog
Input
CLK
OE
D[9:0]
S – 5
S – 6S – 4S – 3S – 2S – 1S1
S2
S3
t
DO
t
DIS
t
EN
Sample 1
Sample 2
89
7
6
5
4
3
2
1


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