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April 10, 2001

79RC5000

JTDO

Output

JTAG Data Out.

Connected directly to JTDI. If no external scan used, this is a no connect.

JTMS

Input

JTAG Command.

Unused input. Should be pulled High.

Initialization interface:

VCCOk

Input

VCC is OK.

When asserted, this signal indicates to the RC5000 that the power supply has been above Vcc minimum for more than 100 milliseconds

and will remain stable. The assertion of VCCOk initiates the reading of the boot-time mode control serial stream.

ColdReset*

Input

Cold Reset.

This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with SysClock.

Reset*

Input

Reset.

This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or syn chro-

nously to initiate a warm reset. Reset must be synchronously de-asserted with SysClock.

ModeClock

Output

Boot Mode Clock.

Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six.

ModeIn

Input

Boot Mode Data In.

Serial boot-mode data input.

BigEndian

Input

Endian mode select.

Allows the system to change the processor addressing mode without rewriting the mode ROM. If endianness is to be specified by using

the BigEndian pin, program mode ROM bit 8 to 0; if endianness is to be specified by the mode ROM, ground the BigEndian pin.

Secondary cache interface:

ScCLR*

Output

Secondary Cache Block Clear.

Clears all valid bits in those Tag RAM’s which support this function.

ScCWE*(1:0)

Output

Secondary Cache Write Enable.

Asserted during writes to the secondary cache

ScDCE*(1:0)

Output

Data RAM Chip Enable.

Chip Enable for Secondary Cache Data RAM

ScDOE*

Input

Data RAM Output Enable.

Asserted by the external agent to enable data onto the SysAD bus

ScLine (15:0)

Output

Data RAM Output Enable.

Cache line index for secondary cache

ScMATCH

Input

Secondary cache Tag Match.

Asserted by Tag RAM on Secondary cache tag match

ScTCE*

Output

Secondary cache Tag RAM Chip Enable.

Chip enable for secondary cache tag RAM.

ScTDE*

Output

Secondary cache Tag RAM Data Enable.

Data Enable for Secondary Cache Tag RAM.

ScTOE*

Output

Secondary cache Tag RAM Output Enable.

Tag RAM Output enable for Secondary Cache Tag RAM’s

ScWord (1:0)

Input/

Output

Secondary cache Word Index.

Determines correct double-word of Secondary cache Index

ScValid

Input/

Output

Secondary cache Valid.

Always driven by the CPU except during a cache probe operation, when it is driven by the tag RAM.

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Table 3: RC5000 Signal Names and Descriptions (Page 2 of 2)