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ISL6726 Datasheet(PDF) 17 Page - Renesas Technology Corp

Part No. ISL6726
Description  Active Clamp Forward PWM Controller
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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ISL6726 Datasheet(HTML) 17 Page - Renesas Technology Corp

 
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ISL6726
FN7654 Rev 0.00
Page 17 of 21
January 31, 2011
Synchronization
ISL6726 provides a single I/O pin synchronization function that
allows synchronization to an external clock or to self-synchronize
to another unit at ~180 degrees out-of-phase for interleaved
applications. When using an external clock, the clock pulse width
must be a minimum of 100ns. The clock frequency must be
higher than the free running frequency of the oscillator.
Multiple units may be synchronized together simply by
connecting the SYNC pins together as shown in Figure 16. In this
configuration all of the devices will synchronize out-of-phase with
the master. The master is usually the unit with the fastest free-
running oscillator, but may not be due to intentional hysteresis
within the arbitration circuitry. Synchronization occurs on the
leading edge of the SYNC signal. However, no unit will accept a
SYNC pulse while its oscillator ramp voltage is less than 3/8 of
the timing capacitor voltage peak voltage. This prevents short
cycling of the period.
If the SYNC pins of multiple devices are connected together, the
first SYNC signal that asserts will reset the oscillator RAMP of all
other devices. Further arbitration may occur if there is a higher
frequency unit present. All slave controllers will operate out-of-
phase with the master. Multiple devices may be synchronized in
this fashion, but the number will depend on the distance and
capacitance of the SYNC signal path. Care should be taken to
ensure the ground potential difference between devices is
minimized. In most cases an external clock is used to
synchronize more than two units.
0.8V
UV
Vpk=0.8UV+0.8
1.6UV/(CTC*RTC)
T1=1/2CTC*RTC
T2=1/8CTC*RTC
DCLIM
T1
T2
TDC= VDC/Vpk*T1
Intrinsic
Maximum D
Maximum D
Set by DCLIM
CS
FIGURE 15. MAXIMUM DUTY CYCLE CLAMP USING DCLIM
FIGURE 16. SYNCHRONIZING TWO UNITS
CT
GND
1
2
4
3
5
6
7
8
19
20
11
12
13
14
15
16
OUTM
ISL6726
9
10
17
18
SYNC
CT
GND
1
2
4
3
5
6
7
8
19
20
11
12
13
14
15
16
OUTM
ISL6726
9
10
17
18
SYNC
OUTM1
OUTM2
OUTM1
OUTM2
CT1
CT2
CT1
CT2


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