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ISL6726 Datasheet(PDF) 15 Page - Renesas Technology Corp |
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ISL6726 Datasheet(HTML) 15 Page - Renesas Technology Corp |
15 / 21 page ISL6726 FN7654 Rev 0.00 Page 15 of 21 January 31, 2011 (VERR) used by the pulse width modulator. Whichever error signal, voltage or current, that commands the lower duty cycle is in control. If the average current is lower than the average current limit threshold, the current error amplifier has no impact on VERR and the voltage loop is in control. If the average current limit threshold is exceeded, however, the current error amplifier will lower VERR to regulate the output current. The voltage loop loses control as it must increase the duty cycle to maintain the output voltage in regulation. After a 100ns leading edge blanking (LEB) delay, the current sense signal is sampled for the duration of the on time, the average current is determined, and the result is amplified by 4x and output to the IOUT pin at the termination of the OUTM pulse. Due to the sampling algorithm used, if an RC filter is placed on the CS input, its time constant should not exceed ~30ns or error may be introduced on IOUT. The average current signal on IOUT produces an accurate representation of the output current provided the converter operates in continuous conduction mode (CCM). Once the inductor current becomes discontinuous (DCM operation), IOUT represents one half of the peak inductor current rather than the average current. This occurs because the sample and hold circuitry is active only during the on time of the switching cycle and cannot determine when the inductor current becomes discontinuous. It is unable to detect when the inductor current reaches zero during the off time. This behavior does not affect the average current limit function, but does have an impact if IOUT is used for current monitoring functions. IOUT may be used with the available error amplifier (EA) of the ISL6726 as shown in Figure 13. The error amplifier is typically configured as an integrator. As shown in Figure 13, IOUT is attenuated by resistors R1 and R2 so that the average current limit threshold can be set independently of the peak current limit threshold. The integrator bandwidth is determined by R and C. The current error amplifier is similar to the voltage EA found in most PWM controllers, except it cannot source current. VERR requires an external pull-up resistor. The IEA is configured as an integrating (Type I) amplifier using ISET as the reference. The voltage applied at FB is integrated against the ISET reference. The resulting signal, VERR, is applied to the PWM comparator where it is compared to the current signal CS. If FB is less than ISET, the IEA will be open loop (can’t source current), VERR will be at a level determined by the voltage loop, and the duty cycle is unaffected. As the output load increases, IOUT will increase, and the voltage applied to FB will increase until it reaches ISET. At this point the IEA will control VERR as required to maintain the output current at the level that corresponds to the ISET reference. When the output current again drops below the average current limit threshold, the IEA returns to an open loop condition, and the duty cycle is again controlled by the voltage loop. The average current control loop behaves much the same as the voltage control loop found in typical power supplies except it regulates current rather than voltage. FIGURE 11. CS INPUT vs IOUT Channel 1: OUTM Channel 2: IOUT Channel 4: CS FIGURE 12. DYNAMIC BEHAVIOR OF CS AND IOUT Channel 1: OUTM Channel 2: IOUT Channel 4: CS FIGURE 13. AVERAGE CURRENT CONFIGURATION + - R R1 R2 C VERR ISET CS 1 2 4 3 5 6 7 8 19 20 11 12 13 14 15 16 IOUT FB ISL6726 9 10 17 18 VREF S&H 4x RPULL-UP |
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Similar Description - ISL6726 |
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