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ISL6726 Datasheet(PDF) 14 Page - Renesas Technology Corp

Part No. ISL6726
Description  Active Clamp Forward PWM Controller
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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ISL6726 Datasheet(HTML) 14 Page - Renesas Technology Corp

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ISL6726
FN7654 Rev 0.00
Page 14 of 21
January 31, 2011
Overlap phasing results when a resistor is connected between
DELAY and GND. Non-overlap phasing results when a resistor is
connected between DELAY and VREF. The resistor value
determines the magnitude of the delay. The delay feature may
be disabled by connecting DELAY directly to GND or VREF,
depending on which configuration is desired, overlap or
non-overlap. The non-overlap time in the overlap mode can be
calculated using Equation 5.
The deadtime in non-overlapping mode can be calculated using
Equation 6.
See Figure 3 for typical DELAY gain curves.
Overcurrent Operation
The ISL6726 has two mechanisms for current limit. The peak
current limit function provides cycle-by-cycle overcurrent
protection. The protection threshold is set by a voltage applied to
ISET. If the peak current at CS exceeds ISET, the OUTM pulse is
terminated for the remainder of the switching cycle.
Peak current limit has some shortcomings that discourage its
use as the only current limit mechanism. First, there is the slope
compensation ramp that adds to the current feedback signal. Its
contribution to the CS signal varies with duty cycle, and at high
duty cycles it has a larger contribution than at lower duty cycles.
As an overload condition causes the duty cycle to decrease, the
portion of the current feedback contributed by the slope
compensation decreases and the amount contributed by the
current feedback increases. The result is that the maximum
output current will increase as the output voltage decreases.
Another phenomenon occurs when the duty cycle is reduced to
the minimum pulse width the IC controller is capable of
producing. If the output voltage is reduced below the value
corresponding to this duty cycle, current tail-out occurs. There is
a certain amount of energy delivered to the output on each
switching cycle that must correspond to voltage and current at
the load. If the voltage is very low due to a shorted output, large
currents can result.
Some controllers solve the problem by allowing the converter to
cycle on and off (hic-cup operation) to lower the average short
circuit current. This works acceptably for some applications, but
not when redundancy or parallel operation is required. Such
behavior can prevent a successful fault recovery when the short
is removed. The paralleled or redundant units will not hic-cup in
unison, and each will experience an overload condition each
time a restart is attempted.
An ideal current limiting method requires a constant value
regardless of the output voltage, the so-called “brick-wall”
current limit. The output current remains constant from current
limit inception to a short circuit. The ISL6726 provides this
behavior with the average current limit function.
The average current limit feature uses a patented circuit that
samples the current feedback signal and creates a signal
proportional to the average value of the output inductor current.
The signal, analogous to the voltage feedback signal of voltage
control loop, becomes the feedback signal for the current error
amplifier and produces a current error signal. The voltage
feedback and current feedback share a common control node
TABLE 1. MODE AND DELAY SETTINGS FOR TYPICAL TOPOLOGIES
TOPOLOGY
MODE
DELAY
PHASING
SOFT-STOP
MINIMUM D CLAMP
N-FET Active Clamp with Diode Rectification
HIGH
R to VREF
Non-OverLap
Disabled
Disabled
P-FET Active Clamp with Diode Rectification
HIGH
R to GND
OverLap
Disabled
Disabled
N-FET Active Clamp with SR Rectification
LOW
R to VREF
Non-OverLap
Enabled
Enabled
P-FET Active Clamp with SR Rectification
LOW
R to GND
OverLap
Enabled
Enabled
Standard Forward with Diode Rectification
HIGH
= 0V,
= VREF
OverLap,
Non-Overlap
Disabled
Disabled
Asymmetric Half-Bridge
LOW
R to VREF
Non-OverLap
Enabled
Enabled
Lm
Tx
+VOUT
+
Vout = Vin*D*Ns/Np
VX
VY
OUTM
IL
IS1
IS2
IS
IMAG
OUTAC
Td = K2*Rdelay
Td = K2*Rdelay
OUTM
FIGURE 10. OUTPUT TIMING DIAGRAM FOR N-CHANNEL ACTIVE
CLAMP
tDELAY
1.83
ns
k
-------- RDELAY k
 13ns
+
=
(EQ. 5)
tDELAY
1.79
ns
k
-------- RDELAY k
 9ns
+
=
(EQ. 6)


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