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ISL6726 Datasheet(PDF) 13 Page - Renesas Technology Corp

Part No. ISL6726
Description  Active Clamp Forward PWM Controller
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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ISL6726 Datasheet(HTML) 13 Page - Renesas Technology Corp

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ISL6726
FN7654 Rev 0.00
Page 13 of 21
January 31, 2011
The soft-stop function is enabled when MODE=0. The ISL6726
enables a soft-stop when UV falls below 1V or when ENABLE is
pulled low (disable), causing a controlled discharge of the SS
capacitor at the rate equal to and opposite of soft-start. Soft-stop
will not occur for a UVLO fault on VDD regardless of the MODE
setting. Soft-stop continues until the SS pin voltage drops below
~0.25V, even if the fault condition is removed before the
threshold is reached.
Using soft-stop forces an orderly shutdown of a converter that
uses synchronous rectification (SR). It prevents the output
voltage from going negative by controlling the rate at which the
output voltage is discharged through the output inductor. It also
prevents the SRs from being avalanched if SR operation is
stopped when the inductor current is negative.
If a self-driven SR method is used, the behavior during turn-off is
improved as well. During soft-stop, the forward rectifier pulse
width is slowly decreased to its minimum while the
free-wheeling rectifier pulse width is slowly increased to its
maximum. The active clamp capacitor voltage, VIN/(1-D),
approaches VIN as the duty cycle approaches zero. The
freewheeling rectifier gate voltage is VIN D/n(1-D), where n is the
transformer turns ratio Np/Ns, and decreases with decreasing
duty cycle. At some point the voltage applied to the gate is
insufficient to turn on the SR FET and negative inductor current
is prevented.
A hard-stop with self-driven SRs results in oscillation of the SRs
because the output voltage can provide gate voltage through the
output inductor and secondary winding.
Minimum Duty Cycle Clamp
In addition to soft-stop when MODE=0, the minimum pulse width
of OUTM is clamped to ~300ns independent of the PWM
modulator. Higher duty cycles are obviously allowed depending on
the operating conditions, but shorter duty cycles are not. In SR
applications, this feature prevents excessive negative output
inductor current if the output should experience a large and
sudden reduction in load, such as occurs during a 100% to 0%
load transient. A sudden load dump can cause the control loop
error voltage to drop sufficiently to command 0% duty cycle. This
sets the forward rectifier to 0% duty cycle and the free-wheeling
rectifier to 100% duty cycle. This condition allows the inductor
current to ramp to a large negative amplitude until the duty cycle
again becomes non-zero. Due to the normal deadtime allowed
for proper switching of the SRs, the forward rectifier will
avalanche when the duty cycle becomes non-zero. When the
forward SR turns on, the inductor current will reflect to the
primary and stress the components there as well. With the
minimum duty cycle clamp feature, the forward rectifier turns on
for ~300ns each cycle and prevents the large negative current in
the output inductor.
Gate Drive
The ISL6726 has two outputs, OUTM and OUTAC. OUTM is
capable of sourcing 1A and sinking 1.5A peak current, and
OUTAC is capable of sourcing 0.5A and sinking 0.75A peak
current. OUTAC is configured using the DELAY input for either
overlap or non-overlap phasing relative to OUTM. When
configured for non-overlap phasing, OUTAC operates at 1-D with
deadtime, where D is the duty cycle of OUTM. This configuration
is useful for the n-channel active clamp and asymmetric half-
bridge topologies. When configured for overlap phasing, OUTAC
has symmetric rising edge advance and falling edge delays
relative to OUTM. This configuration is useful for the p-channel
active clamp topology.
Two typical active clamp converter configurations are shown in
Figures 9 and 10, with overlap or non-overlap delay time
accurately set by a programming resistor. The rising edge
overlap and the falling edge overlap time (or rising edge
deadtime, and falling edge deadtime) are equal and
independent of the operating frequency or duty cycle.
To limit the peak current through the IC, an external resistor may
be placed in series between an output and the gate of the
MOSFET. The resistor also dampens any oscillation caused by
the resonant tank of the parasitic inductance of the PWB traces
and the FET gate input capacitance. The overlap/non-overlap
delay between OUTAC and OUTM prevents simultaneous
conduction of the main and clamp switches in an active clamp
converter, or the upper and lower switches in an asymmetric
half- bridge converter.
Table 1 shows the combinations of the settings with the
corresponding features for different topologies.
1.2(VERR-VOFFSET)
0.27V
VSS=5V-ISS*t/CSS
0.0V
OUTM
OUTAC
CS
Soft-stop begins
Soft-stop ends
FIGURE 8. SOFT-STOP FUNCTION (IDELAY POSITIVE)
OUTAC
Lm
Tx
+VOUT
+
Vout = Vin*D*Ns/Np
VX
VY
OUTM
OUTAC
OUTM
D
Td = K1*Rdelay
Td = K1*Rdelay
FIGURE 9. OUTPUT TIMING DIAGRAM FOR P-CHANNEL ACTIVE
CLAMP


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