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ISL6726 Datasheet(PDF) 12 Page - Renesas Technology Corp

Part No. ISL6726
Description  Active Clamp Forward PWM Controller
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com

ISL6726 Datasheet(HTML) 12 Page - Renesas Technology Corp

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FN7654 Rev 0.00
Page 12 of 21
January 31, 2011
Functional Description
The ISL6726 PWM is an excellent choice for low cost high
performance applications requiring D (duty cycle) and 1-D
control signals. This includes active clamp forward, asymmetric
half-bridge, and synchronous rectified (SR) standard forward and
flyback topologies. Among its many features are:
• High current FET drivers
• Adjustable soft-start and soft-stop
•Slope compensation
• Programmable deadtime control
• Overlapping and non-overlapping output configuration for both
n-channel and p-channel clamp configurations
• Peak and average overcurrent protection
• Internal thermal protection
• Minimum duty cycle clamp
• Input voltage dependent maximum duty cycle clamp
Supply Currents
The total supply current, IDD, will be dependent on the load applied
to outputs OUTM and OUTAC. Total IDD current is the sum of the
quiescent current and the average output current. Knowing the
operating frequency (FSW) and the output loading capacitance
charge (Q) per output, the average output current can be calculated
from Equation 1:
The ISL6726 oscillator has a programmable frequency range to
2MHz, and can be set with one resistor and one capacitor. The
use of two timing elements, RTC, and CT allow great flexibility
and precision when setting the oscillator frequency.
The switching period is the sum of the timing capacitor charge
and discharge durations. The charge and discharge duration is
determined by RTC and CT.
Where tC and tD are the charge and discharge times,
respectively, tSW is the oscillator free running period, and FSW is
the oscillator frequency. The actual times will be slightly longer
than calculated due to internal propagation delays of
approximately 10ns/transition. This delay adds directly to the
switching duration, but also causes overshoot of the timing
capacitor peak and valley voltage thresholds, effectively
increasing the peak-to-peak voltage on the timing capacitor.
Additionally, if very low charge and discharge currents are used,
there will be increased error due to the input impedance of the
CT pin.
The timing component tolerance directly effects the oscillator
accuracy. A NPO/COG dielectric ceramic capacitor or better is
suggested for CT. RTC should be 1% tolerance or better.
Figure 1 graphically portrays the oscillator frequency as function
of the timing components. The minimum deadtime is fixed at
20% of the period allowing an 80% maximum duty cycle. This
limits the maximum voltage stress on the power MOSFETs to 5x
the input voltage. For applications that cannot tolerate this
voltage stress, the maximum duty cycle can be reduced using
the DCLIM feature. The peak voltage stress for an active clamp
topology is approximately VIN/(1-D).
Soft-Start/Soft-Stop Operation
The ISL6726 features a soft-start using an external capacitor in
conjunction with an internal current source. Soft-start reduces
stresses and surge currents during start-up. Soft-stop reduces
electrical stresses during shutdown when synchronous rectifiers
(SRs) are used and prevents polarity reversal of the converter
output. Soft-stop may be inhibited with MODE for applications
not using SRs.
The soft-start feature clamps the duty cycle for the duration of
soft-start. The duty cycle is initially forced to zero and allowed to
linearly increase until the control loop takes control. At the
beginning of a soft-start cycle, the SS capacitor is discharged. If
ENABLE is open and there is no UVLO fault on VDD, a current
source charges the soft-start capacitor. Taking into account the
internal gains and offsets of VERR and SS, soft-start limits the
peak current amplitude as long as it remains below VERR. As
the SS voltage increases, the peak current amplitude is allowed
to increase. The output pulse width increases accordingly, until
the SS voltage exceeds VERR and the control loop takes over.
The SS voltage will continue to increase until it reaches its clamp
voltage of 4.6V even though soft-start is actually finished when
the control loop takes over. The duty cycle increases from zero to
its steady state operating point during the soft-start period. The
soft-start waveform is shown in Figure 7 for the non-overlap
configuration, appropriate for the active clamp forward with a
n-channel clamp FET or the asymmetric half-bridge topology. For
the active clamp topology using a p-channel clamp FET, the
overlap configuration is required and the OUTAC waveform
shown in Figure 7 would be inverted. The non-overlap
configuration is shown for clarity.
(EQ. 1)
tC 0.5 RTC
(EQ. 2)
tD 0.125 RTC
(EQ. 3)
(EQ. 4)
Soft-start ends
Soft-start begins

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