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ISL6726 Datasheet(PDF) 3 Page - Renesas Technology Corp
RENESAS [Renesas Technology Corp]
ISL6726 Datasheet(HTML) 3 Page - Renesas Technology Corp
/ 21 page
FN7654 Rev 0.00
Page 3 of 21
January 31, 2011
A slope compensation capacitor is connected between SLOPE and GND. A current source of 100µA charges the capacitor during
the On time and discharges it during the Off time. The amplitude of the signal is multiplied by a gain of 0.2 and summed with the
The Active Clamp output for driving an external power switch. OUTAC is capable of driving either a p- or n- channel clamp device and
is configured by DELAY.
VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the
VDD and GND pins as possible. VDD is monitored for undervoltage (UVLO). When VDD is below the UVLO threshold, the IC is disabled
and the reference voltage, VREF, is turned off.
The main PWM output for driving an external power switch.
Logic and power ground for this device. Due to high peak currents and high frequency operation, a low impedance layout is
necessary. Ground planes and short traces are highly recommended.
The 5.00V reference voltage output having a -2/+1.5% tolerance over line, load and operating temperature. Bypass to GND
with a 0.1µF to 2.2µF low ESR capacitor. VREF can source up to 10mA.
The DELAY pin configures OUTAC for either n-channel or p-channel drive compatibility by setting the phase and the duration when
both the main and active clamp outputs are off. A resistor from DELAY to VREF sets an out-of-phase (non-overlap) relationship for
an n-channel clamp device with adjustable deadtime. A resistor from DELAY to GND sets an in-phase (overlap) relationship for a
p-channel clamp device with an adjustable symmetric non-overlap duration between OUTM and OUTAC.
The MODE pin configures the IC for standard or synchronous rectification operation. If MODE is connected to VREF, standard
rectification operation is selected. Soft-stop and the minimum duty cycle clamp are disabled. If MODE is connected to GND,
synchronous rectification operation is enabled allowing soft-stop and the minimum duty cycle clamp to function.
Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start and soft-stop. The value of the
SS capacitor determines the rate of increase and decrease of the duty cycle during start-up and soft-stop. Soft-stop is
enabled/disabled by MODE.
(Notes 1, 2, 3)
-40 to +105
20 Ld QSOP
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6726. For more information on MSL, please see Technical Brief TB363.
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