W523AXXX

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5.4 CPU Interface

The W523Axxx can communicate with an external microprocessor through a simple serial CPU

interface. The CPU interface consists of TG1, TG2 and STPA/BUSY pins, which are shown below:

Debounced OK. to clear the internal CPU

counter for preventing the system from

running away. (TG1F should be disabled.)

END

TG1

(Data)

TG2

(Clock)

STPA/Busy

AUD/SPK+

Notes:

µS.

3. The "Clock" frequency of the TG2 pin can be set in the range: 10 KHz - 1 MHz.

Busy signal will output "high" after the end of transmission. The rising timing of Busy signal is

dependent on the MSB of data output on TG1 (Data) pin. If MSB is "1", Busy will rise after the last

rising edge of TG2 (Clock) pin. If MSB is "0", Busy will rise after the rising edge that TG1 (Data)

returns to high.

TG1

(DATA)

TG2

(CLK)

BUSY

7 bits

MSB=0

40ns

TG1

(DATA)

TG2

(CLK)

BUSY

7 bits

MSB=1

40ns