Electronic Components Datasheet Search |
|
W523A008 Datasheet(PDF) 10 Page - Winbond |
|
W523A008 Datasheet(HTML) 10 Page - Winbond |
10 / 19 page W523AXXX - 10 - 5.4 CPU Interface The W523Axxx can communicate with an external microprocessor through a simple serial CPU interface. The CPU interface consists of TG1, TG2 and STPA/BUSY pins, which are shown below: Debounced OK. to clear the internal CPU counter for preventing the system from running away. (TG1F should be disabled.) TDEB END TCRD TG1 (Data) TG2 (Clock) STPA/Busy AUD/SPK+ Notes: 1. TDEB means the "Debounce time". 2. TCRD is the "CPU Reset Delay" time. This should be more than 2.6 µS. 3. The "Clock" frequency of the TG2 pin can be set in the range: 10 KHz - 1 MHz. Busy signal will output "high" after the end of transmission. The rising timing of Busy signal is dependent on the MSB of data output on TG1 (Data) pin. If MSB is "1", Busy will rise after the last rising edge of TG2 (Clock) pin. If MSB is "0", Busy will rise after the rising edge that TG1 (Data) returns to high. TG1 (DATA) TG2 (CLK) BUSY 7 bits MSB=0 40ns TG1 (DATA) TG2 (CLK) BUSY 7 bits MSB=1 40ns |
Similar Part No. - W523A008 |
|
Similar Description - W523A008 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |