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ISL6552 Datasheet(PDF) 11 Page - Renesas Technology Corp

Part No. ISL6552
Description  Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL6552 Datasheet(HTML) 11 Page - Renesas Technology Corp

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ISL6552
FN4918 Rev 2.00
Page 11 of 18
July 2004
conditions that caused the over-voltage still persist, the PWM
outputs will be cycled between three state and VCORE
clamped to ground, as a hysteretic shunt regulator.
Under-Voltage
The VSEN pin also detects when the CORE voltage falls more
than 10% below the VID programmed level. This causes
PGOOD to go low, but has no other effect on operation and is
not latched. There is also hysteresis in this detection point.
Over-Current
In the event of an over-current condition, the over-current
protection circuit reduces the RMS current delivered to 41% of
the current limit. When an over-current condition is detected,
the controller forces all PWM outputs into a three state mode.
This condition results in the gate driver removing drive to the
output stages. The ISL6552 goes into a wait delay timing cycle
that is equal to the Soft-Start ramp time. PGOOD also goes
“low” during this time due to VSEN going below its threshold
voltage. To lower the average output dissipation, the Soft-Start
initial wait time is increased from 32 to 2048 cycles, then the
Soft-Start ramp is initiated. At a PWM frequency of 200kHz, for
instance, an over-current detection would cause a dead time of
10.24ms, then a ramp of 10.08ms.
At the end of the delay, PWM outputs are restarted and the soft
start ramp is initiated. If a short is present at that time, the cycle
is repeated. This is the hiccup mode.
Figure 6 shows the supply shorted under operation and the
hiccup operating mode described above. Note that due to the
high short circuit current, over-current is detected before
completion of the start-up sequence so the delay is not quite
as long as the normal Soft-Start cycle.
CORE Voltage Programming
The voltage identification pins (VID0, VID1, VID3, and
VID25mV) set the CORE output voltage. Each VID pin is pulled
to VCC by an internal 20
A current source and accepts open-
collector/open-drain/open-switch-to-ground or standard low-
voltage TTL or CMOS signals.
Table 1 shows the nominal DAC voltage as a function of the
VID codes. The power supply system is
1% accurate over the
operating temperature and voltage range.
PGOOD
SHORT
50A/DIV
CURRENT
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
SUPPLY FREQUENCY = 200kHz, V IN = 12V
HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY
CORE LOAD CURRENT = 31A, 5V LOAD = 5A
SHORT APPLIED HERE
FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP
TABLE 1. VOLTAGE IDENTIFICATION CODES
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
VCCCORE
(VDC)
VID25mV
VID3
VID2
VID1
VID0
0
0100
1.05
1
0100
1.075
0
0011
1.10
1
0011
1.125
0
0010
1.15
1
0010
1.175
0
0001
1.20
1
0001
1.225
0
0000
1.25
1
0000
1.275
0
1111
1.30
1
1111
1.325
0
1110
1.35
1
1110
1.375
0
1101
1.40
1
1101
1.425
0
1100
1.45
1
1100
1.475
0
1011
1.50
1
1011
1.525
0
1010
1.55
1
1010
1.575
0
1001
1.60
1
1001
1.625
0
1000
1.65
1
1000
1.675
0
0111
1.70
1
0111
1.725
0
0110
1.75
1
0110
1.775
0
0101
1.80
1
0101
1.825


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