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ISL6552 Datasheet(PDF) 9 Page - Renesas Technology Corp |
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ISL6552 Datasheet(HTML) 9 Page - Renesas Technology Corp |
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9 / 18 page  ISL6552 FN4918 Rev 2.00 Page 9 of 18 July 2004 output pulse width of the comparator to compensate for the detected “above average” current in that channel. Droop Compensation In addition to control of each power channel’s output current, the average channel current is also used to provide CORE voltage “droop” compensation. Average full channel current is defined as 50 A. By selecting an input resistor, RIN, the amount of voltage droop required at full load current can be programmed. The average current driven into the FB pin results in a voltage increase across resistor RIN that is in the direction to make the error amplifier “see” a higher voltage at the inverting input, resulting in the error amplifier adjusting the output voltage lower. The voltage developed across RIN is equal to the “droop” voltage. See the “Current Sensing and Balancing” section for more details. Applications and Converter Start-Up Each PWM power channel’s current is regulated. This enables the PWM channels to accurately share the load current for enhanced reliability. The HIP6601, HIP6602 or HIP6603 MOSFET driver interfaces with the ISL6552. For more information, see the HIP6601, HIP6602 or HIP6603 data sheets [1][2]. The ISL6552 is capable of controlling up to 4 PWM power channels. Connecting unused PWM outputs to VCC automatically sets the number of channels. The phase relationship between the channels is 360o/number of active PWM channels. For example, for three channel operation, the PWM outputs are separated by 120o. Figure 2 shows the PWM output signals for a four channel system. Power supply ripple frequency is determined by the channel frequency, FSW, multiplied by the number of active channels. For example, if the channel frequency is set to 250kHz and there are three phases, the ripple frequency is 750kHz. The IC monitors and precisely regulates the CORE voltage of a microprocessor. After initial start-up, the controller also provides protection for the load and the power supply. The following section discusses these features. Initialization The ISL6552 usually operates from an ATX power supply. Many functions are initiated by the rising supply voltage to the VCC pin of the ISL6552. Oscillator, sawtooth generator, soft- start and other functions are initialized during this interval. These circuits are controlled by POR, Power-On Reset. During this interval, the PWM outputs are driven to a three state condition that makes these outputs essentially open. This state results in no gate drive to the output MOSFETs. Once the VCC voltage reaches 4.375V (+125mV), a voltage level to insure proper internal function, the PWM outputs are enabled and the Soft-Start sequence is initiated. If for any reason, the VCC voltage drops below 3.875V (+125mV). The POR circuit shuts the converter down and again three states the PWM outputs. Soft-Start After the POR function is completed with VCC reaching 4.375V, the Soft-Start sequence is initiated. Soft-Start, by its slow rise in CORE voltage from zero, avoids an over-current condition by slowly charging the discharged output capacitors. This voltage rise is initiated by an internal DAC that slowly raises the reference voltage to the error amplifier input. The voltage rise is controlled by the oscillator frequency and the DAC within the ISL6552, therefore, the output voltage is effectively regulated as it rises to the final programmed CORE voltage value. For the first 32 PWM switching cycles, the DAC output remains inhibited and the PWM outputs remain three stated. From the 33rd cycle and for another, approximately 150 cycles the PWM output remains low, clamping the lower output MOSFETs to ground, see Figure 3. The time variability is due to the error amplifier, sawtooth generator and comparators moving into their active regions. After this short interval, the PWM outputs are enabled and increment the PWM pulse width from zero duty cycle to operational pulse width, thus allowing the output voltage to slowly reach the CORE voltage. The CORE voltage will reach its programmed value before the 2048 cycles, but the PGOOD output will not be initiated until the 2048th PWM switching cycle. The Soft-Start time or delay time, DT = 2048/FSW. For an oscillator frequency, FSW, of 200kHz, the first 32 cycles or 160 s, the PWM outputs are held in a three state level as explained above. After this period and a short interval described above, the PWM outputs are initiated and the voltage rises in 10.08ms, for a total delay time DT of 10.24ms. Figure 3 shows the start-up sequence as initiated by a fast rising 5V supply, VCC, applied to the ISL6552. Note the short PWM 1 PWM 2 PWM 3 PWM 4 FIGURE 2. FOUR PHASE PWM OUTPUT AT 500kHz |
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