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UJA1061 Datasheet(PDF) 44 Page - NXP Semiconductors |
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UJA1061 Datasheet(HTML) 44 Page - NXP Semiconductors |
44 / 81 page 2004 Mar 22 44 Philips Semiconductors Objective specification Low speed CAN/LIN system basis chip UJA1061 6.14.8 SYSTEM CONFIGURATION REGISTER This register, only accessible in Normal and Standby modes, allows the UJA1061 behaviour to be configured. Table 9 SC - System Configuration register (address 10) bit description Note 1. For fail-safe reasons, this bit is set automatically when entering the Reset state. BIT SYMBOL DESCRIPTION VALUE FUNCTION 15, 14 A1, A0 register address 10 select System Configuration register 13 RRS Read Register Select 1 read the General Purpose Feedback register (GPF0) 0 read the System Configuration Feedback register (SCF) 12 RO Read Only 1 read register selected by RRS without writing to System Configuration register 0 read register selected by RRS and write to System Configuration register 11 − reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 10 − reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 9 GSTHC GND Shift Threshold Control 1 −1.5 V; exceeding this level forces an interrupt 0 −0.75 V; exceeding this level forces an interrupt 8 RLC Reset Length Control 1(1) 20 ms system reset is selected; default after power-up 0 1 ms system reset is selected 7, 6 V3C V3 Control 11 Cyclic mode 2; 350 µs ON/32 ms period 10 Cyclic mode 1; 350 µs ON/16 ms period 01 continuously ON 00 OFF; also reset to 00 in Fail-safe mode, or after a negative edge has been detected at the external RSTN pin, or a short-circuit situation is detected at V3 5 V1RTHC V1 Reset Threshold Control 1 the reduced V1 undervoltage threshold is selected 0 the normal V1 undervoltage threshold is selected 4 V1CMC V1 Current Monitor Control 1 an increasing V1 current causes a reset event if the watchdog was disabled during Standby mode 0 an increasing V1 current just activates the watchdog again during Standby mode 3 WEN WAKE Enable 1 wake-up functionality at WAKE pin enabled 0 wake-up functionality at WAKE pin disabled 2 WSC WAKE Sample Control 1 WAKE mode cyclic sample 0 WAKE mode continuous sample 1 − reserved 0 reserved for future use; should always be set to logic 0 in order to secure compatibility with future functions which will be activated by a logic 1 0 IC INH control 1 INH/LIMP home pin HIGH 0 INH/LIMP home pin floating |
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