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HIP6303 Datasheet(PDF) 9 Page - Renesas Technology Corp

Part No. HIP6303
Description  Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HIP6303 Datasheet(HTML) 9 Page - Renesas Technology Corp

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HIP6303
FN4767 Rev.0.00
Page 9 of 16
December 1999
described above, the PWM outputs are initiated and the
voltage rises in 10.08ms, for a total delay time DT of 10.24ms.
Figure 3 shows the start-up sequence as initiated by a fast
rising 5V supply, VCC, applied to the HIP6303. Note the short
rise to the three state level in PWM 1 output during first 32
PWM cycles.
Figure 4 shows the waveforms when the regulator is operating
at 200kHz. Note that the Soft-Start duration is a function of the
Channel Frequency as explained previously. Also note the
pulses on the COMP terminal. These pulses are the current
correction signal feeding into the comparator input (see the
Block Diagram
on page 2).
Figure 5 shows the regulator operating from an ATX supply. In
this figure, note the slight rise in PGOOD as the 5V supply
rises.The PGOOD output stage is made up of NMOS and
PMOS transistors. On the rising VCC, the PMOS device
becomes active slightly before the NMOS transistor pulls
“down”, generating the slight rise in the PGOOD voltage.
.
Note that Figure 5 shows the 12V gate driver voltage available
before the 5V supply to the HIP6303 has reached its threshold
level. If conditions were reversed and the 5V supply was to rise
first, the start-up sequence would be different. In this case the
HIP6303 will sense an over-current condition due to charging
the output capacitors. The supply will then restart and go
through the normal Soft-Start cycle.
Fault Protection
The HIP6303 protects the microprocessor and the entire power
system from damaging stress levels. Within the HIP6303 both
Over-Voltage and Over-Current circuits are incorporated to
protect the load and regulator.
Over-Voltage
The VSEN pin is connected to the microprocessor CORE
voltage. A CORE over-voltage condition is detected when the
VSEN pin goes more than 15% above the programmed VID
level.
The over-voltage condition is latched, disabling normal PWM
operation, and causing PGOOD to go low. The latch can only
be reset by lowering and returning VCC high to initiate a POR
and Soft-Start sequence.
During a latched over-voltage, the PWM outputs will be driven
either low or three state, depending upon the VSEN input.
PWM outputs are driven low when the VSEN pin detects that
the CORE voltage is 15% above the programmed VID level.
This condition drives the PWM outputs low, resulting in the
lower or synchronous rectifier MOSFETS to conduct and shunt
the CORE voltage to ground to protect the load.
PWM 1
PGOOD
VCORE
5V
OUTPUT
VCC
VIN = 12V
DELAY TIME
FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT
500kHz
PGOOD
VCORE
5V
V COMP
VCC
VIN = 12V
DELAY TIME
FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT
200kHz
12V ATX
SUPPLY
PGOOD
5 V ATX
VCORE
SUPPLY
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
VIN = 5V, CORE LOAD CURRENT = 31A
FIGURE 5. SUPPLY POWERED BY ATX SUPPLY
FREQUENCY 200kHZ


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