HIP6018B

FN4586 Rev 3.00

Page 7 of 15

April 1, 2005

Description

Operation

The HIP6018B monitors and precisely controls 4 output

voltage levels (Refer to Figures 1, 2, and 3). It is designed for

microprocessor computer applications with 3.3V and 5V

power, and 12V bias input from an ATX power supply. The IC

has one PWM controller, a linear controller, and a linear

regulator. The PWM controller is designed to regulate the

(Q1 and Q2) in a synchronous-rectified buck converter

configuration. The core voltage is regulated to a level

programmed by the 5-bit digital-to-analog converter (DAC). An

integrated linear regulator supplies the 2.5V clock power

Initialization

The HIP6018B automatically initializes upon receipt of input

power. Special sequencing of the input supplies is not

necessary. The Power-On Reset (POR) function continually

monitors the input supply voltages. The POR monitors the bias

on the OCSET1 pin, and the 3.3V input on the VIN2 pin. The

drop (see over-current protection). The POR function initiates

soft-start operation after all three input supply voltages exceed

their POR thresholds.

Soft-Start

The POR function initiates the soft-start sequence. Initially, the

voltage on the SS pin rapidly increases to approximately 1V

(this minimizes the soft-start interval). Then an internal 11

A

pin to 4V. The PWM error amplifier reference input (+terminal)

and output (COMP1 pin) is clamped to a level proportional to

the SS pin voltage. As the SS pin voltage slews from 1V to 4V,

the output clamp generates PHASE pulses of increasing width

that charge the output capacitor(s). After this initial stage, the

reference input clamp slows the output voltage rate-of-rise and

provides a smooth transition to the final set voltage.

Additionally both linear regulator’s reference inputs are

clamped to a voltage proportional to the SS pin voltage. This

method provides a rapid and controlled output voltage rise.

Figure 3 shows the soft-start sequence for the typical

application. At T0 the SS voltage rapidly increases to

approximately 1V. At T1, the SS pin and error amplifier output

voltage reach the valley of the oscillator’s triangle wave. The

oscillator’s triangular waveform is compared to the clamped

error amplifier output voltage. As the SS pin voltage increases,

the pulse-width on the PHASE pin increases. The interval of

increasing pulse-width continues until each output reaches

sufficient voltage to transfer control to the input reference

time occurs at T2. During the interval between T2 and T3, the

error amplifier reference ramps to the final value and the

converter regulates the output to a voltage proportional to the

SS pin voltage. At T3 the input clamp voltage exceeds the

reference voltage and the output voltage is in regulation.

The remaining outputs are also programmed to follow the SS

follows a ramp similar to that of the PWM output. When each

output reaches sufficient voltage the input reference clamp

slows the rate of output voltage rise. The PGOOD signal

toggles ‘high’ when all output voltage levels have exceeded

their under-voltage levels. See the Soft-Start Interval section

under Applications Guidelines for a procedure to determine the

soft-start interval.

Fault Protection

All three outputs are monitored and protected against extreme

overload. A sustained overload on any linear regulator output

or an over-voltage on the PWM output disables all converters

and drives the FAULT pin to VCC.

Figure 7 shows a simplified schematic of the fault logic. An over-

voltage detected on VSEN1 immediately sets the fault latch. A

sequence of three over-current fault signals also sets the fault

signal), such that an under-voltage event on either linear output

(FB2 or FB3) is ignored until after the soft-start interval (T4 in

over increased time intervals, without generating a fault. Cycling

resets the counter and the fault latch.

Over-Voltage Protection

FIGURE 6. SOFT-START INTERVAL

0V

0V

0V

TIME

PGOOD

SOFT-START

(1V/DIV)

OUTPUT

(0.5V/DIV)

VOLTAGES

T1

T2

T3

T0

(2V/DIV)

T4