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CMV20000 Datasheet(PDF) 11 Page - ams AG |
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CMV20000 Datasheet(HTML) 11 Page - ams AG |
11 / 48 page Reference:CMV20000-datasheet-v2.3 CMV20000 Datasheet Page 10 of 47 © 2015 CMOSIS bvba 3.4 ELECTRICAL IO SPECIFICATIONS 3.4.1 DIGITAL IO CMOS/TTL DC SPECIFICATIONS Parameter Description Conditions min typ max Units VIH High level input voltage 2.0 VDD33 V VIL Low level input voltage GND 0.8 V VOH High level output voltage VDD=3.3V IOH=-2mA 2.4 V VOL Low level output voltage VDD=3.3V IOL=2mA 0.4 V 3.4.2 LVDS RECEIVER SPECIFICATIONS Parameter Description Conditions min typ max Units VID Differential input voltage Steady state 100 350 600 mV VIC Receiver input range Steady state 0.0 2.4 V IID Receiver input current VINP|INN=1.2V±50mV, 0≤ VINP|INN≤2.4V 20 µA ∆IID Receiver input current difference |IINP – IINN| 6 µA 3.4.3 LVDS DRIVER SPECIFICATIONS Parameter Description Conditions min typ max Units VOD Differential output voltage Steady State, RL = 100Ω 247 350 454 mV ∆VOD Difference in VOD between complementary output states Steady State, RL = 100Ω 50 mV VOC Common mode voltage Steady State, RL = 100Ω 1.125 1.25 1.375 V ∆VOC Difference in VOC between complementary output states Steady State, RL = 100Ω 50 mV IOS,GND Output short circuit current to ground VOUTP=VOUTN=GND 24 mA IOS,PN Output short circuit current VOUTP=VOUTN 12 mA 3.5 INPUT CLOCK The high speed LVDS input clock (LVDS_CLK_N/P) defines the output data rate of the CMV20000. The master clock (CLK_IN) must be 12 times slower and this clock but is optional. The maximum data rate of the output is 480Mbps which results in a LVDS_CLK_N/P of 480MHz (and a CLK_IN of 40MHz). The minimum frequencies are 10MHz for CLK_IN and 120MHz for LVDS_CLK_N/P. Any frequency between the minimum and maximum can be applied by the user and will result in a corresponding output data rate. |
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