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SN74LV20ADBR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LV20ADBR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 13 page SN54LV20A, SN74LV20A DUAL 4INPUT POSITIVENAND GATE SCES339E − SEPTEMBER 2000 − REVISED APRIL 2005 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D 2-V to 5.5-V VCC Operation D Max tpd of 6 ns at 5 V D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information These dual 4-input positive-NAND gates are designed for 2-V to 5.5-V VCC operation. The ’LV20A devices perform the Boolean function Y = A • B • C • D or Y = A + B + C + D in positive logic. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC − D Tube of 50 SN74LV20AD LV20A SOIC − D Reel of 2500 SN74LV20ADR LV20A SOP − NS Reel of 2000 SN74LV20ANSR 74LV20A −40 °C to 85°C SSOP − DB Reel of 2000 SN74LV20ADBR LV20A −40 °C to 85°C Tube of 90 SN74LV20APW TSSOP − PW Reel of 2000 SN74LV20APWR LV20A TSSOP − PW Reel of 250 SN74LV20APWT LV20A TVSOP − DGV Reel of 2000 SN74LV20ADGVR LV20A CDIP − J Tube of 25 SNJ54LV20AJ SNJ54LV20AJ −55 °C to 125°C CFP − W Tube of 150 SNJ54LV20AW SNJ54LV20AW −55 C to 125 C LCCC − FK Tube of 55 SNJ54LV20AFK SNJ54LV20AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2005, Texas Instruments Incorporated SN54LV20A ...FK PACKAGE (TOP VIEW) SN54LV20A ...J OR W PACKAGE SN74LV20A ... D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) NC − No internal connection 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 1B NC 1C 1D 1Y GND VCC 2D 2C NC 2B 2A 2Y 32 1 20 19 910 11 1213 4 5 6 7 8 18 17 16 15 14 2C NC NC NC 2B NC NC 1C NC 1D Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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