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PSB21373 Datasheet(PDF) 58 Page - Infineon Technologies AG |
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PSB21373 Datasheet(HTML) 58 Page - Infineon Technologies AG |
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58 / 242 page  PSB 21373 Data Sheet 58 2002-05-13 2.2.5 C/I Channel Handling The Command/Indication channel carries real-time status information between the SCOUT-DX and another device connected to the IOM. 1) One C/I channel (called C/I0) conveys the commands and indications between the layer-1 and the layer-2 parts of the SCOUT-DX. It can be accessed by an external layer- 2 device e.g. to control the layer-1 activation/deactivation procedures. C/I0 channel access may be arbitrated via the TIC bus access protocol. In this case the arbitration is done in C/I channel 2 (see figure 11). The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer-2) and register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four bits long. A listing and explanation of the layer-1 C/I codes can be found in chapter 2.3.4.1.3 and 2.3.4.1.6. In the receive direction, the code from layer-1 is continuously monitored, with an interrupt being generated anytime a change occurs (ISTA.CIC). A new code must be found in two consecutive IOM frames to be considered valid and to trigger a C/ I code change interrupt status (double last look criterion). In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0. 2) A second C/I channel (called C/I1) can be used to convey real time status information between the SCOUT-DX and various non-layer-1 peripheral devices e.g. PSB 2161 ARCOFI-BA. The C/I1 channel consists of four or six bits in each direction.The width can be changed from 4bit to 6bit by setting bit CIX1.CICW. The C/I1 channel is accessed via registers CIR1 and CIX1. A change in the received C/I1 code is indicated by an interrupt status without double last look criterion. 2.2.5.1 CIC Interrupt Logic Figure 28 shows the CIC interrupt structure. A CIC interrupt may originate – from a change in received C/I channel 0 code (CIC0) or – from a change in received C/I channel 1 code (CIC1). The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case the occurrence of a code change in CIR1 will not be displayed by CIC1 until the corresponding enable bit has been set to one. Bits CIC0 and CIC1 are cleared by a read of CIR0. An interrupt status is issued every time a valid new code is loaded into CIR0 or CIR1. The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the received C/I channel 0 before the first one has been read, immediately after reading of CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several |
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