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ISL8002B Datasheet(PDF) 20 Page - Renesas Technology Corp |
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ISL8002B Datasheet(HTML) 20 Page - Renesas Technology Corp |
20 / 22 page ISL8002B FN8690 Rev 3.00 Page 20 of 22 October 28, 2016 Output Capacitor Selection An output capacitor is required to filter the inductor current. Output ripple voltage and transient response are two critical factors when considering output capacitance choice. The current mode control loop allows for the use of low ESR ceramic capacitors and thus smaller board layout. Electrolytic and polymer capacitors may also be used. Additional consideration applies to ceramic capacitors. While they offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. Ceramic capacitors are rated using large peak-to-peak voltage swings and with no DC bias. In the DC/DC converter application, these conditions do not reflect reality. As a result, the actual capacitance may be considerably lower than the advertised value. Consult the manufacturers datasheet to determine the actual in-application capacitance. Most manufacturers publish capacitance vs DC bias so that this effect can be easily accommodated. The effects of AC voltage are not frequently published, but an assumption of ~20% further reduction will generally suffice. The result of these considerations can easily result in an effective capacitance 50% lower than the rated value. Nonetheless, they are a very good choice in many applications due to their reliability and extremely low ESR. Equations 6 and 7 allow calculation of the required capacitance to meet a desired ripple voltage level. Additional capacitance may be used. For the ceramic capacitors (low ESR) = where I is the inductor’s peak-to-peak ripple current, fSW is the switching frequency and COUT is the output capacitor. If using electrolytic capacitors then: Regarding transient response needs, a good starting point is to determine the allowable overshoot in VOUT if the load is suddenly removed. In this case, energy stored in the inductor will be transferred to COUT causing its voltage to rise. After calculating capacitance required for both ripple and transient needs, choose the larger of the calculated values. Equation 8 determines the required output capacitor value in order to achieve a desired overshoot relative to the regulated voltage. where VOUTMAX/VOUT is the relative maximum overshoot allowed during the removal of the load. For an overshoot of 5%, Equation 8 becomes Equation 9 Layout Considerations The PCB layout is a very important converter design step to make sure the designed converter works well. The power loop is composed of the output inductor L’s, the output capacitor COUT, the PHASE’s pins and the PGND pin. It is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short, and wide. The switching node of the converter, the PHASE pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. The input capacitor should be placed as close as possible to the VIN pin and the ground of the input and output capacitors should be connected as close as possible. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for better EMI performance. It is recommended to add at least four vias ground connection within the pad for the best thermal relief. VOUTripple I 8fSWCOUT ------------------------------------- = (EQ. 6) VOUTripple I*ESR = (EQ. 7) (EQ. 8) COUT IOUT2*L VOUT2* VOUTMAX VOUT 2 1 – -------------------------------------------------------------------------------------------- = COUT IOUT2*L VOUT 2 * 1.05 2 1 – ----------------------------------------------------- = (EQ. 9) |
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