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PC7447VG1200N Datasheet(PDF) 7 Page - ATMEL Corporation |
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PC7447VG1200N Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 66 page  7 PC7457/47 [Preliminary] 5345B–HIREL–02/04 – MESI data cache coherency maintained in hardware – Separate copy of data cache tags for efficient snooping – Parity support on cache and tags – No snooping of instruction cache except for icbi instruction – Data cache supports AltiVec LRU and transient instructions – Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding • Level 2 (L2) cache interface – On-chip, 512 Kbyte, eight-way set-associative unified instruction and data cache – Fully pipelined to provide 32 bytes per clock cycle to the L1 caches – A total nine-cycle load latency for an L1 data cache miss that hits in L2 – PLRU replacement algorithm – Cache write-back or write-through operation programmable on a per-page or per-block basis – 64-byte, two-sectored line size – Parity support on cache • Level 3 (L3) cache interface (not implemented on PC7447) – Provides critical double-word forwarding to the requesting unit – Internal L3 cache controller and tags – External data SRAMs – Support for 1, 2, and 4M bytes (MB) total SRAM space – Support for 1 or 2 MB of cache space – Cache write-back or write-through operation programmable on a per-page or per-block basis – 64-byte (1 MB) or 128-byte (2 MB) sectored line size – Private memory capability for half (1 MB minimum) or all of the L3 SRAM space for a total of 1-, 2-, or 4-MB of private memory – Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelined synchronous Burst SRAMs, and pipelined (register-register) Late Write synchronous Burst SRAMs – Supports parity on cache and tags – Configurable core-to-L3 frequency divisors – 64-bit external L3 data bus sustains 64-bit per L3 clock cycle • Separate memory management units (MMUs) for Instructions and data – 52-bit virtual address; 32- or 36-bit physical address – Address translation for 4 Kbyte pages, variable-sized blocks, and 256M bytes segments – Memory programmable as write-back/write-through, caching- inhibited/caching-allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis – Separate IBATs and DBATs (eight each) also defined as SPRs |
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