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DRV8306HRSMT Datasheet(PDF) 7 Page - Texas Instruments

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Part # DRV8306HRSMT
Description  38-V Brushless DC Motor Controller
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DRV8306HRSMT Datasheet(HTML) 7 Page - Texas Instruments

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7
DRV8306
www.ti.com
SLVSE38 – APRIL 2018
Product Folder Links: DRV8306
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Electrical Characteristics (continued)
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(2)
Errata: The current silicon has a typical value of 40 mV (Hall comparator hysteresis voltage - VHYS).
(3)
Errata: The current silicon has a min/max value of ±10 mV (Hall comparator hysteresis difference - ΔVHYS).
IDRIVEP
Peak source gate current (high-side
and low-side)
IDRIVE tied to AGND
15
mA
IDRIVE 18 kΩ (±5%) to AGND
45
IDRIVE 75 kΩ (±5%) to AGND
60
IDRIVE Hi-Z ( > 500 kΩ to AGND)
90
IDRIVE 75 kΩ (±5%) to DVDD
105
IDRIVE 18 kΩ (±5%) to DVDD
135
IDRIVE tied to DVDD
150
IDRIVEN
Peak sink gate current (high-side and
low-side)
IDRIVE tied to AGND
30
mA
IDRIVE 18 kΩ (±5%) to AGND
90
IDRIVE 75 kΩ (±5%) to AGND
120
IDRIVE Hi-Z ( > 500 kΩ to AGND)
180
IDRIVE 75 kΩ (±5%) to DVDD
210
IDRIVE 18 kΩ (±5%) to DVDD
270
IDRIVE tied to DVDD
300
IHOLD
FET holding current
Source current after tDRIVE
15
mA
Sink current after tDRIVE
30
ISTRONG
FET hold-off strong pulldown
GHX and GLX
300
mA
ROFF
FET gate hold-off resistor
GHX to SHX and GLX to PGND
150
HALL SENSOR INPUTS (HPX, HNX)
VHYS
Hall comparator hysteresis voltage
25(2)
mV
ΔVHYS
Hall comparator hysteresis difference
Between A, B and C
–5(3)
5(3)
mV
VID
Hall comparator input differential
50
mV
VCM
(1)
Hall comparator input common mode
voltage CM range
1.5
3.5
V
II
Input leakage current
H_x+= H_x-
–1
1
µA
tHDEG
Hall deglitch time
5
µs
CYCLE-BY-CYCLE CURRENT LIMIT (ISEN)
VLIMIT
Voltage limit across RSENSE for the
current limiter
0.225
0.25
0.275
V
tBLANK
Time that VLIMIT is ignored from the
start of the PWM cycle
5
µs
PROTECTION CIRCUITS
VUVLO
VM undervoltage lockout
VM falling, UVLO report
5.4
5.8
V
VM rising, UVLO recovery
5.6
6
VUVLO_HYS
VM undervoltage hysteresis
Rising to falling threshold
200
mV
tUVLO_DEG
(1)
VM undervoltage deglitch time
VM falling, UVLO report
10
µs
VCPUV
Charge pump undervoltage
With respect to VM
2.4
V
VGS_CLAMP
Gate drive clamping voltage
Positive clamping voltage
10.5
15
V
Negative clamping voltage
–0.6


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