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DRV8306HRSMT Datasheet(PDF) 6 Page - Texas Instruments |
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DRV8306HRSMT Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 37 page  6 DRV8306 SLVSE38 – APRIL 2018 www.ti.com Product Folder Links: DRV8306 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tWAKE Wake-up time VVM > VUVLO; ENABLE = 3.3 V to output transistion 1 ms VDVDD Internal logic regulator voltage IDVDD = 0 to 30 mA 2.9 3.3 3.6 V CHARGE PUMP (VCP, CPH, CPL) VVCP VCP operating voltage with respect to VM VM = 12 to 38 V; IVCP = 0 to 15 mA 7 10 11.5 V VM = 10 V; IVCP = 0 to 10 mA 6.5 7.5 9.5 V VM = 8 V; IVCP = 0 to 5 mA 5 6 7.5 V VM = 6 V; IVCP = 0 to 1 mA 3.8 4.3 6.5 V LOGIC-LEVEL INPUTS (PWM, DIR, nBRAKE) VIL Input logic low voltage 0 0.8 V VIH Input logic high voltage 1.5 5.5 V VHYS Input logic hysteresis 100 mV IIL Input logic low current VIN = 0 V –1 1 µA IIH Input logic high current VIN = 5 V 100 µA RPD Pulldown resistance (PWM, DIR, nBRAKE) Internal pulldown to AGND 100 kΩ tPD Propagation delay INHX/INLX tansition to GHX/GLX transition 180 250 ns LOGIC-LEVEL INPUTS (ENABLE) VIL Input logic low voltage 0 0.6 V VIH Input logic high voltage 1.5 5.5 V VHYS Input logic hysteresis 100 mV IIL Input logic low current VIN = 0 V –10 10 µA IIH Input logic high current VIN = 5 V –5 5 µA SEVEN-LEVEL INPUTS (IDRIVE, VDS) VI1 Input mode 1 voltage Tied to AGND 0 V VI2 Input mode 2 voltage 18 kΩ ± 5% to AGND 0.5 V VI3 Input mode 3 voltage 75 kΩ ± 5% to AGND 1.1 V VI4 Input mode 4 voltage Hi-Z 1.65 V VI5 Input mode 5 voltage 75 kΩ ± 5% to DVDD 2.2 V VI6 Input mode 6 voltage 18 kΩ ± 5% to DVDD 2.8 V VI7 Input mode 7 voltage Tied to DVDD 3.3 V OPEN-DRAIN OUTPUTS (nFAULT, FGOUT) VOL Output logic low voltage IOD = 2 mA 0.1 V IOZ Output logic high current VOD = 5 V –1 1 µA GATE DRIVERS (GHX, SHX, GLX) VGHS (1) High-side VGS gate drive (gate-to- source) VVM = 12 to 38 V; IHS_GATE = 0 to 15 mA 7 10 11.5 V VVM = 10 V; IHS_GATE = 0 to 10 mA 6.5 7.5 8.5 VVM = 8 V; IHS_GATE = 0 to 5 mA 5 6 7 VVM = 6 V; IHS_GATE = 0 to 1 mA 3.8 4.3 6.5 VGSL (1) Low-side VGS gate drive (gate-to- source) VVM = 12 to 38 V; ILS_GATE = 0 to 15 mA 7.5 10 12.5 V VVM = 10 V; ILS_GATE = 0 to 10 mA 5.5 7.5 9.5 VVM = 8 V; ILS_GATE = 0 to 5 mA 3.5 6 8.5 VVM = 6 V; ILS_GATE = 0 to 1 mA 3 4.3 6.5 tDEAD Output dead time 120 ns tDRIVE Peak gate drive time 4000 ns |
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