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DP83TC811S-Q1 Datasheet(PDF) 6 Page - Texas Instruments |
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DP83TC811S-Q1 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 143 page 6 DP83TC811S-Q1 SNLS579 – APRIL 2018 www.ti.com Product Folder Links: DP83TC811S-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Pin Functions(1) (continued) PIN STATE(2) DESCRIPTION NAME NO. SERIAL MANAGEMENT INTERFACE MDC 1 I Management Data Clock: Synchronous clock to the MDIO serial management input and output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz. There is no minimum clock rate. MDIO 36 IO Management Data Input/Output: Bidirectional management data signal that may be sourced by the management station or the PHY. This pin requires a pullup resistor. Recommended to use a resistor between 2.2 kΩ and 9 kΩ. CONTROL INTERFACE INT 2 PU, OD, O Interrupt: Active-LOW output, which will be asserted LOW when an interrupt condition occurs. This pin has a weak internal pullup. Register access is necessary to enable various interrupt triggers. Once an interrupt event flag is set, register access is required to clear the interrupt event. Note: Power-on-RESET (POR) Done interrupt is enabled by default. POR Done interrupt can be cleared by reading register INT_STAT3 Register 0x0018 – Interrupt Status Register #3. This pin can be configured as an Active-HIGH output using register INT_TEST Register 0x0011 – Interrupt Test Register. RESET 3 PU, I Reset: Active-LOW input, which initializes or reinitializes the DP83TC811S-Q1. Asserting this pin LOW for at least 1 μs will force a reset process to occur. All internal registers will reinitialize to their default states as specified for each bit in the Register Maps section. All bootstrap pins are resampled upon deassertion of reset. EN 7 PD, I Enable: Active-HIGH input, which will disable the DP83TC811S-Q1 when pulled LOW and power down all internal blocks. Disable state is equivalent to a power-down state. This pin can be directly tied to VDDIO; enabling the device. WAKE 8 PD, I WAKE: Active-HIGH input, which wakes the PHY from SLEEP. Asserting this pin HIGH at power-up will prevent the PHY from going to SLEEP. This pin can be directly tied to VDDIO to wake the device. INH 10 O INH: Active-HIGH output, which will be asserted HIGH when the PHY is in SLEEP or DISABLED. This pin is LOW for all other PHY states. CLOCK INTERFACE XI 5 I Reference Clock Input (MII / RGMII / SGMII): Reference clock 25-MHz ±100 ppm-tolerance crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only and XO left floating. Reference Clock Input (RMII): Reference clock 50-MHz ±100 ppm-tolerance CMOS-level oscillator in RMII Slave mode. Reference clock 25-MHz ±100 ppm-tolerance crystal or oscillator in RMII Master mode. This is a fail-safe pin. When the PHY is not powered, an external oscillator is allowed to be powered and driving into this pin. Fail-safe prevents pin back-driving. XO 4 O Reference Clock Output: XO pin is used for crystal only. This pin should be left floating when a CMOS-level oscillator is connected to XI. LED/GPIO INTERFACE LED_0 / GPIO_0 35 S, PD, IO LED_0: Link Status LED_1 / GPIO_1 6 S, PD, IO LED_1: Link Status and BLINK for TX/RX Activity CLKOUT / GPIO_2 16 IO Clock Output: 25-MHz reference clock MEDIUM DEPENDENT INTERFACE TRD_M 13 IO Differential Transmit and Receive: Bidirectional differential signaling configured for 100BASE-T1 operation, IEEE 802.3bw compliant. TRD_P 12 JTAG (IEEE 1149.1) TCK 17 PU, I Test Clock: Primary clock source for all test logic input and output. This pin is controlled by the testing entity. This pin can be left unconnected if not used. |
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