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PC7457VGU933L Datasheet(PDF) 3 Page - ATMEL Corporation |
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PC7457VGU933L Datasheet(HTML) 3 Page - ATMEL Corporation |
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3 / 66 page  + Integer Reservation Station Unit 2 + Integer Reservation Station Unit 2 Additional Features - Time Base Counter/Decrementer - Clock Multiplier - JTAG/COP Interface - Thermal/Power Management - Performance Monitor PA Instruction Unit Instruction Queue (12-Word) 96-Bit (3 Instructions) Reservation 128-Bit (4 Instructions) 32-Bit FPSCR FPSCR + x ÷ Floating- Point Unit 64-Bit Reservation 32-Bit Completion Unit Completion Queue (16-Entry) 32-Kbyte D Cache 36-Bit 64-Bit Stations (2) Station Reservation v Stations (2) FPR File 16 Rename Buffers Stations (2-Entry) GPR File 16 Rename Buffers Reservation Station VR File 16 Rename Buffers 64-Bit 128-Bit Completes up Instruction MMU SRs 128-Entry IBAT Array ITLB Tags 32-Kbyte I Cache Vector Touch Queue VR Issue FPR Issue Branch Processing Unit CTR LR BTIC (128-Entry) BHT (2048-Entry) Fetcher GPR Issue (6-Entry/3-Issue) (4-Entry/2-Issue) (2-Entry/1-Issue) Dispatch Unit Data MMU SRs (Original) 128-Entry DBAT Array DTLB 32-Bit EA Status L2 Store Queue (L2SQ) Vector FPU Reservation Station Reservation v Station Reservation Station Vector Integer er Unit 1 Vector Integer er Unit 2 Vector Permute Unit Line Tags Block 0 (32-Byte) Status Block 1 (32-Byte) Memory Subsystem Snoop Push/ Interventions L1 Castouts Bus Accumulator (4) x ÷ Integer Unit 2 to three per clock instructions L1 Load Queue (LLQ) L1 Load Miss (5) Cacheable Store Request(1) L1 Service L1 Store Queue (LSQ) L3 Cache Controller(1) L3CR Status Tags Bus Accumulator Block 0/1 Line System Bus Interface L2 Prefetch (3) 64-Bit Data (8-Bit Parity) External SRAM Address Bus Data Bus Queues Castout Bus Store Queue Push Load Queue (11) Queue (9)/ Queue (10)(2) Notes: 1. The L3 cache interface is not implemented on the PC7447. 2. The Castout Queue and Push Queue share resources such for a combined total of 10 entries. The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push. 512-Kbyte UniÞed L2 Cache Controller 19-Bit Address (1, 2, or 4 Mbytes) Tags Instruction Fetch (2) 128-Bit Reservation (Shadow) + Load/Store Unit (EA Calculation) Finished Completed Stores Stores Load Miss L1 Castout L1 Push Vector Touch Engine + Integer (3) Unit 1 |
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