Electronic Components Datasheet Search |
|
STM48-1V0S100-7Z Datasheet(PDF) 19 Page - Bel Fuse Inc. |
|
STM48-1V0S100-7Z Datasheet(HTML) 19 Page - Bel Fuse Inc. |
19 / 30 page STM48-MAIN STM48-SATELLITE Rev. 1.0 – 21/02/2018 www.powerstamp.org Page 19 of 30 belfuse.com/power-solutions SVID / AVS Interface The MAIN Power Stamp supports alternatively Intel Serial VID interface (SVID) or PMBus Adaptive Voltage Scaling interface (AVS) for output voltage positioning. The SVID interface communicates with Intel microprocessor through three wires, SVCLK, SVDAT, and SV_ALRT, and controls the VID code change rate. It is fully compliant with Intel VR13 PWM rev 1.1, document # 544905 and Intel SVID protocol Rev1.7, document # 456098. To guarantee proper device and CPU operations, refer to these documents for bus design and layout guidelines. Different platforms may require different pull-up impedance on the bus. Please contact Intel for detailed information regarding the SVID interface. FPGAs, ASICs, SoCs and non-Intel processors can adaptively change their supply voltages using AVS. The SVID and AVS interfaces share the same hardware and switching between the two can happen at run time. The corresponding AVS pin names are AVSCLK, AVSMDAT and AVSSDAT. Paralleling The block diagram of the MAIN Power Stamp digital control loop is illustrated in the figure: MAIN PWM2Y PWM1X PWM1Y PWM2X PWM3X PWM3Y PWM4X G2 G1 H2 H1 J2 J1 K2 Digital Multi-cell Controller CSN4 CSP5 CSP6 CSN5 CSN6 F6 E3 F3 E7 F7 Primary parallel bus PWM6X PWM4Y PWM5X PWM5Y PWM6Y START3 START4 K1 L2 L1 L3 M3 N4 N6 START5 START6 M4 DPWM Secondary parallel bus START2 N5 N3 Digital COT control PID DPS Remote buffer CSP2 CSN2 CSN3 CSP3 CSP4 E5 F5 E4 F4 E6 Secondary parallel bus Secondary parallel bus ADC DAC E8 F8 Vref Temperature sensor +S -S + + - + - Digital current sharing Temp. comp. droop The converter output voltage is differentially sensed by the +S and –S inputs of the remote buffer and compared with a digitally adjustable voltage reference Vref. The output of the remote buffer is summed to a temperature compensated (TMP) droop signal for load line generation and converted by the analog to digital converter (ADC) into digital. Digital PID compensation is then applied before the signal is transmitted to the digital constant on time (COT) control. Output currents of each individual phase are differentially sensed by the CSN and CSP inputs. A digital current sharing block drives the digital COT control. Input voltage feedforward is applied to the digital COT control via the VRSMON signal. Dynamic Phase Shedding (DPS) is computed as a function of the output current conditions and concurs |
Similar Part No. - STM48-1V0S100-7Z |
|
Similar Description - STM48-1V0S100-7Z |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |