STM48-MAIN

STM48-SATELLITE

Rev. 1.0 – 21/02/2018

www.powerstamp.org

Page 17 of 30

belfuse.com/power-solutions

Feature Description - MAIN

The MAIN Power Stamp is a standalone DC-DC PoL converter designed to control multi-phase, interleaved arrays of

SATELLITE Power Stamps. It includes an on-board SATELLITE and an STPSA60 Digital Multi-cell Controller in a single

package. MAIN and SATELLITE are using the same pinout for signals available in both modules. The MAIN module

additionally includes an LGA connector for control signals not present on SATELLITE. A single MAIN can control up to

five SATELLITE for an array of six phases, maximum. Several digital interfaces are included for ease of integration into

complex microprocessor applications.

Primary Microcontroller Interface

The digital multi-cell controller embedded in the MAIN Power Stamp monitors input/output voltage, power and

current in order to manage OV, UV and OC events and to provide telemetry data to the CPU and PMBus interfaces.

The Primary Microcontroller Interface (PuC I/F) transmits information about the telemetry from the primary side.

Either digital or analog transmission methods are available. A serial interface is conveniently used in isolated

configurations (PUCDTO, PUCDTI, PUCCK and PUCCS pins) with external digital isolators. Non-isolated configurations

can take advantage of the analog VRSMON signal. User can program how and when to use such configurations and

telemetry data information. Following standard PMBus implementation, each protection features a programmable

warning and fault limits and actions. Protections are configurable and used to trigger special outputs of the CPU

interface. Please refer to the STPSA60 Data Sheet and GUI User Manual for a list of the specific commands supported.

MAIN

VR_RDY

PFAULT_IN#

VR_HOT#

FAULT#

VCCIO_OK

PIN_ALERT#

EN

D1

K7

L4

L5

L7

L8

L6

Digital Multi-cell

Controller

IRQ

PuC

I/F

PUCDTO

PUCDTI

PUCCS

PUCCK

E1

E2

F1

F2

PuC I/F

CPU I/F

CPU Interface

The EN pin is an active-high signal that enables the converter when pulled up to VCC, connect to GND to disable.

Please contact Intel for detailed information regarding the CPU interface and a list of the specific signals supported.

PMBus Interface

The MAIN Power Stamp has a PMBus interface that supports both communication and control. The PMBus Power

Management Protocol Specification can be obtained from www.pmbus.org. The modules support a subset of version

1.2 of the standard and is fully compatible with the PMBus™ specification for read/write access in the byte, word,

block mode. More than 110 commands are implemented, covering all the basic and advanced functions of the device.