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K11P121M50SF4V2 Datasheet(PDF) 49 Page - NXP Semiconductors

Part # K11P121M50SF4V2
Description  Kinetis K11D Sub-Family
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

K11P121M50SF4V2 Datasheet(HTML) 49 Page - NXP Semiconductors

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Table 39. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
Characteristic
Min.
Max.
Unit
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
75
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
S1
S2
S2
S3
S4
S4
S5
S9
S7
S9
S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 23. I2S/SAI timing — master modes
Table 40. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
87
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
30
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid1 —
72
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
I2S switching specifications
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
49
Freescale Semiconductor, Inc.


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