K11P121M50SF4V2 datasheet(44/65 Pages) NXP

Part #	K11P121M50SF4V2

Description	Kinetis K11D Sub-Family

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Table 34. Slave mode DSPI timing (limited voltage range) (continued)

Num

Description

Min.

Max.

Unit

DS9

DSPI_SCK input cycle time

4 x tBUS

—

ns

DS10

DSPI_SCK input high/low time

(tSCK/2) − 2

(tSCK/2) + 2

ns

DS11

DSPI_SCK to DSPI_SOUT valid

—

10

ns

DS12

DSPI_SCK to DSPI_SOUT invalid

0

—

ns

DS13

DSPI_SIN to DSPI_SCK input setup

2

—

ns

DS14

DSPI_SCK to DSPI_SIN input hold

7

—

ns

DS15

DSPI_SS active to DSPI_SOUT driven

—

14

ns

DS16

DSPI_SS inactive to DSPI_SOUT not driven

—

14

ns

First data

Last data

First data

Data

Last data

Data

DS15

DS10

DS9

DS16

DS11

DS12

DS14

DS13

DSPI_SS

DSPI_SCK

(CPOL=0)

DSPI_SOUT

DSPI_SIN

Figure 18. DSPI classic SPI timing — slave mode

3.8.2 DSPI switching specifications (full voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The

tables below provides DSPI timing characteristics for classic SPI timing modes. Refer

to the DSPI chapter of the Reference Manual for information on the modified transfer

formats used for communicating with slower peripheral devices.

Table 35. Master mode DSPI timing (full voltage range)

Num

Description

Min.

Max.

Unit

Notes

Operating voltage

1.71

3.6

V

1

Frequency of operation

—

12.5

MHz

DS1

DSPI_SCK output cycle time

4 x tBUS

—

ns

DS2

DSPI_SCK output high/low time

(tSCK/2) - 4

(tSCK/2) + 4

ns

Table continues on the next page...

Peripheral operating requirements and behaviors

44

Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.

Freescale Semiconductor, Inc.

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