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K11P121M50SF4V2 Datasheet(PDF) 30 Page - NXP Semiconductors

Part # K11P121M50SF4V2
Description  Kinetis K11D Sub-Family
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

K11P121M50SF4V2 Datasheet(HTML) 30 Page - NXP Semiconductors

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Table 22. NVM reliability specifications (continued)
Symbol
Description
Min.
Typ.1
Max.
Unit
Notes
nnvmcycp Cycling endurance
10 K
50 K
cycles
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
5
50
years
tnvmretd1k Data retention after up to 1 K cycles
20
100
years
nnvmcycd Cycling endurance
10 K
50 K
cycles
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
50
years
tnvmretee10 Data retention up to 10% of write endurance
20
100
years
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree4k
Write endurance
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio =
4096
35 K
315 K
1.27 M
10 M
175 K
1.6 M
6.4 M
50 M
writes
writes
writes
writes
3
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ °C.
3. Write endurance represents the number of writes to each FlexRAM location at -40 °C ≤Tj ≤ °C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and
typical values assume all byte-writes to FlexRAM.
3.4.2 EzPort switching specifications
Table 23. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
ns
EP7
EZP_CK low to EZP_Q output valid
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
ns
EP9
EZP_CS negation to EZP_Q tri-state
12
ns
Peripheral operating requirements and behaviors
30
Kinetis K11D Sub-Family Data Sheet, Rev6, 04/2014.
Freescale Semiconductor, Inc.


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