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NCV8141D2TG Datasheet(PDF) 8 Page - ON Semiconductor |
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NCV8141D2TG Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 12 page NCV8141 http://onsemi.com 8 APPLICATION NOTES NCV8141 DESIGN EXAMPLE The NCV8141 with its unique integration of linear regulator and control features: RESET, ENABLE and WATCHDOG, provides a single IC solution for a microprocessor power supply. The reset delay, reset duration and watchdog frequency limit are all determined by a single capacitor. For a particular microprocessor the overriding requirement is usually the reset delay (also known as power on reset). The capacitor is chosen to meet this requirement and the reset duration and watchdog frequency follow. The reset delay is given by: tPOR(typ) + (4.75 105)CDELAY Assume that the reset delay must be 200 ms minimum. From the NCV8141 data sheet the reset delay has a $37% tolerance due to the regulator. Assume the capacitor tolerance is $10%. tPOR(min) + (4.75 105 0.63) CDELAY 0.9 CDELAY(min) + tPOR(min) 2.69 105 CDELAY(min) + 0.743 mF Closest standard value is 0.82 mF. Minimum and maximum delays using 0.82 mF are 220 ms and 586 ms. The duration of the reset pulse is given by: TWDI(RESET)(typ) + (1.0 104) CDELAY This has a tolerance of ±50% due to the IC, and ±10% due to the capacitor. The duration of the reset pulse ranges from 3.69 ms to 13.5 ms. The watchdog signal can be expressed as a frequency or time. From a programmers point of view, time is more useful since they must ensure that a watchdog signal is issued consistently several times per second. The watchdog time is given by: tWDI + (1.3 105)CDELAY There is a tolerance of ±20% due to the NCV8141. With a capacitor tolerance of ±10%: tWDI + (1.3 105) 1.2 1.1 CDelay tWDI + 141 ms (max) tWDI + (1.3 105) 0.8 0.9 CDELAY tWDI + 76 ms (min) The software must be written so that a watchdog signal arrives at least every 76 ms. Figure 9. WDI Signal for CDelay = 0.82 mF using NCV8141 Hz ms 7 FAIL 13 141 76 PASS ENERGY CONSERVATION AND SMART FEATURES Energy conservation is another benefit of using a regulator with integrated microprocessor control features. Using the NCV8141 as indicated in Figure 10, the microprocessor can control its own power down sequence. The momentary contact switch quickly charges C1 through R1. When the voltage across C1 reaches 3.95 V ( the enable threshold), the output switches on and VOUT rises to 5.0 V. After a delay period determined by CDelay, a frequency programmable reset pulse train is generated at the reset output. The pulse train continues until the correct watchdog signal appears at the WDI lead. C1 is now left to discharge through the input impedance of the enable lead (approximately 150 k W) and the enable signal disappears. The output voltage remains at 5.0 V as long as the NCV8141 continues to receive the correct watchdog signal. The microprocessor can power itself down by terminating its watchdog signal. When the microprocessor finishes its housekeeping or power down software routine, it stops sending a watchdog signal. In response, the regulator generates a reset signal and goes into a sleep mode where VOUT drops to 0 V, shutting down the microprocessor. |
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