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M36L0T7050T0 Datasheet(PDF) 6 Page - STMicroelectronics |
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M36L0T7050T0 Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 18 page M36L0T7050T0, M36L0T7050B0 6/18 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A22). Addresses A0-A20 are common inputs for the Flash Memory and the PSRAM components. The other lines (A21-A22) are inputs for the Flash Memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. Dur- ing Bus Write operations they control the com- mands sent to the Command Interface of the Flash memory Program/Erase Controller or they select the cells to access in the PSRAM. The Flash memory component is accessed through the Chip Enable signal (EF) and through the Write Enable (WF) signal, while the PSRAM is accessed through two Chip Enable signals (E1P and E2P) and the Write Enable signal (WP). Data Input/Output (DQ0-DQ15). In the Flash memory the Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Write Bus operation. In the PSRAM the Upper Byte Data Inputs/Out- puts, DQ8-DQ15, carry the data to or from the up- per part of the selected address during a Write or Read operation, when Upper Byte Enable (UBP) is driven Low. The Lower Byte Data Inputs/Outputs, DQ0-DQ7, carry the data to or from the lower part of the se- lected address during a Write or Read operation, when Lower Byte Enable (LBP) is driven Low. Flash Chip Enable (EF). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip En- able is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. Flash Output Enable (GF). The Output Enable input controls data output during Flash memory Bus Read operations. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and ad- dress inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M30L0T7000T0 datasheet). Flash Reset (RPF). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 7., Flash DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is re- set. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transi- tion of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic with- out any additional circuitry. It can be tied to VRPH (refer to Table 8., Flash Memory DC Characteris- tics - Voltages). Flash Latch Enable (LF). Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Flash Clock (KF). The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, accord- ing to the configuration settings) when Latch En- able is at VIL. Clock is don't care during Asynchronous Read and in write operations. Flash Wait (WAITF). WAIT is a Flash output sig- nal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at VIH or Flash Reset is at VIL. It can be config- ured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable. Chip Enable (E1P). When asserted (Low), the Chip Enable, E1P, activates the memory state ma- chine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. Chip Enable (E2P). The Chip Enable, E2P, puts the device in Power-down mode (Deep Power- Down, PAR and Standby) when it is driven Low. One of these, Deep Power-Down mode, is the low- est power mode. Output Enable (GP). The Output Enable, GP, provides a high speed tri-state control, allowing |
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