Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

M36L0T7050T0 Datasheet(PDF) 6 Page - STMicroelectronics

Part # M36L0T7050T0
Description  128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32Mbit (2M x16) PSRAM, Multi-Chip Package
Download  18 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M36L0T7050T0 Datasheet(HTML) 6 Page - STMicroelectronics

Back Button M36L0T7050T0 Datasheet HTML 2Page - STMicroelectronics M36L0T7050T0 Datasheet HTML 3Page - STMicroelectronics M36L0T7050T0 Datasheet HTML 4Page - STMicroelectronics M36L0T7050T0 Datasheet HTML 5Page - STMicroelectronics M36L0T7050T0 Datasheet HTML 6Page - STMicroelectronics M36L0T7050T0 Datasheet HTML 7Page - STMicroelectronics M36L0T7050T0 Datasheet HTML 8Page - STMicroelectronics M36L0T7050T0 Datasheet HTML 9Page - STMicroelectronics M36L0T7050T0 Datasheet HTML 10Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 18 page
background image
M36L0T7050T0, M36L0T7050B0
6/18
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A22). Addresses
A0-A20
are common inputs for the Flash Memory and the
PSRAM components. The other lines (A21-A22)
are inputs for the Flash Memory component only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the Flash
memory Program/Erase Controller or they select
the cells to access in the PSRAM.
The Flash memory component is accessed
through the Chip Enable signal (EF) and through
the Write Enable (WF) signal, while the PSRAM is
accessed through two Chip Enable signals (E1P
and E2P) and the Write Enable signal (WP).
Data Input/Output (DQ0-DQ15). In
the
Flash
memory the Data I/O output the data stored at the
selected address during a Bus Read operation or
input a command or the data to be programmed
during a Write Bus operation.
In the PSRAM the Upper Byte Data Inputs/Out-
puts, DQ8-DQ15, carry the data to or from the up-
per part of the selected address during a Write or
Read operation, when Upper Byte Enable (UBP) is
driven Low.
The Lower Byte Data Inputs/Outputs, DQ0-DQ7,
carry the data to or from the lower part of the se-
lected address during a Write or Read operation,
when Lower Byte Enable (LBP) is driven Low.
Flash Chip Enable (EF). The Chip Enable input
activates the memory control logic, input buffers,
decoders and sense amplifiers. When Chip En-
able is Low, VIL, and Reset is High, VIH, the device
is in active mode. When Chip Enable is at VIH the
Flash memory is deselected, the outputs are high
impedance and the power consumption is reduced
to the standby level.
Flash Output Enable (GF). The Output Enable
input controls data output during Flash memory
Bus Read operations.
Flash Write Enable (WF). The
Write
Enable
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is Low, VIL,
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, VIH, Lock-Down is
disabled and the Locked-Down blocks can be
locked or unlocked. (See the Lock Status Table in
the M30L0T7000T0 datasheet).
Flash Reset (RPF). The Reset input provides a
hardware reset of the memory. When Reset is at
VIL, the memory is in Reset mode: the outputs are
high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to
Table 7., Flash DC Characteristics - Currents, for
the value of IDD2. After Reset all blocks are in the
Locked state and the Configuration Register is re-
set. When Reset is at VIH, the device is in normal
operation. Exiting Reset mode the device enters
Asynchronous Read mode, but a negative transi-
tion of Chip Enable or Latch Enable is required to
ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to VRPH
(refer to Table 8., Flash Memory DC Characteris-
tics - Voltages).
Flash Latch Enable (LF). Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, VIL,
and it is inhibited when Latch Enable is High, VIH.
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (KF). The Clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at VIL. Clock is don't care during
Asynchronous Read and in write operations.
Flash Wait (WAITF). WAIT is a Flash output sig-
nal used during Synchronous Read to indicate
whether the data on the output bus are valid. This
output is high impedance when Flash Chip Enable
is at VIH or Flash Reset is at VIL. It can be config-
ured to be active during the wait cycle or one clock
cycle in advance. The WAITF signal is not gated
by Output Enable.
Chip Enable (E1P). When asserted (Low), the
Chip Enable, E1P, activates the memory state ma-
chine, address buffers and decoders, allowing
Read and Write operations to be performed. When
de-asserted (High), all other pins are ignored, and
the device is put, automatically, in low-power
Standby mode.
Chip Enable (E2P). The Chip Enable, E2P, puts
the device in Power-down mode (Deep Power-
Down, PAR and Standby) when it is driven Low.
One of these, Deep Power-Down mode, is the low-
est power mode.
Output Enable (GP). The Output Enable, GP,
provides a high speed tri-state control, allowing


Similar Part No. - M36L0T7050T0

ManufacturerPart #DatasheetDescription
logo
Numonyx B.V
M36L0T7050T2 NUMONYX-M36L0T7050T2 Datasheet
442Kb / 22P
   128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
M36L0T7050T2ZAQ NUMONYX-M36L0T7050T2ZAQ Datasheet
442Kb / 22P
   128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
M36L0T7050T2ZAQE NUMONYX-M36L0T7050T2ZAQE Datasheet
442Kb / 22P
   128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
M36L0T7050T2ZAQF NUMONYX-M36L0T7050T2ZAQF Datasheet
442Kb / 22P
   128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
M36L0T7050T2ZAQT NUMONYX-M36L0T7050T2ZAQT Datasheet
442Kb / 22P
   128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
More results

Similar Description - M36L0T7050T0

ManufacturerPart #DatasheetDescription
logo
STMicroelectronics
M36L0R7050T0 STMICROELECTRONICS-M36L0R7050T0 Datasheet
406Kb / 18P
   128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package
M36P0R9070E0 STMICROELECTRONICS-M36P0R9070E0 Datasheet
200Kb / 26P
   512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
M36P0R9060E0 STMICROELECTRONICS-M36P0R9060E0 Datasheet
203Kb / 23P
   512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 64 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package
M36P0R9070E0 STMICROELECTRONICS-M36P0R9070E0_06 Datasheet
214Kb / 23P
   512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 128 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package
logo
Numonyx B.V
M36P0R9060E0 NUMONYX-M36P0R9060E0 Datasheet
459Kb / 23P
   512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 64 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package
M36P0R9070E0 NUMONYX-M36P0R9070E0 Datasheet
468Kb / 23P
   512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 128 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package
M36L0T7050T2 NUMONYX-M36L0T7050T2 Datasheet
442Kb / 22P
   128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
logo
STMicroelectronics
M36L0R8060T0 STMICROELECTRONICS-M36L0R8060T0 Datasheet
358Kb / 18P
   256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
logo
Numonyx B.V
M36P0R9060N0 NUMONYX-M36P0R9060N0 Datasheet
454Kb / 23P
   512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 64 Mbit (Burst) PSRAM, 1.8V supply, Mux I/O, Multi-Chip Package
logo
STMicroelectronics
M36L0R8060T1 STMICROELECTRONICS-M36L0R8060T1 Datasheet
390Kb / 18P
   256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com