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ADC12DL3200ACF Datasheet(PDF) 7 Page - Texas Instruments |
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ADC12DL3200ACF Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 122 page  7 ADC12DL3200 www.ti.com SLVSDR3 – MAY 2018 Product Folder Links: ADC12DL3200 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NO. NAME G8 VD11 I 1.1-V digital supply G9 DACLK+ O LVDS output for data clock of LVDS bus A. Positive connection. This pin can be left disconnected if not used. G10 DACLK– O LVDS output for data clock of LVDS bus A. Negative connection. This pin can be left disconnected if not used. G11 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply G12 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply G13 DC6+ O LVDS output for bit 6 of LVDS bus C. Positive connection. This pin can be left disconnected if not used. G14 DC6– O LVDS output for bit 6 of LVDS bus C. Negative connection. This pin can be left disconnected if not used. G15 DCCLK+ O LVDS output for data clock of LVDS bus C. Positive connection. This pin can be left disconnected if not used. G16 DCCLK– O LVDS output for data clock of LVDS bus C. Negative connection. This pin can be left disconnected if not used. H1 CLK+ I Device (sampling) clock positive input. TI strongly recommends that the clock signal be AC-coupled to this input for best performance. In single-channel mode, the analog input signal is sampled on both rising and falling edges. In-dual channel mode, the analog signal is sampled on the rising edge. This differential input has an internal untrimmed 100-Ω differential termination and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is set to 0. H2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. H3 VA19 I 1.9-V analog supply H4 VA19 I 1.9-V analog supply H5 VA19 I 1.9-V analog supply H6 VA19 I 1.9-V analog supply H7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. H8 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. H9 DASTR+ O LVDS output for data strobe of LVDS bus A. Positive connection. This pin can be left disconnected if not used. H10 DASTR– O LVDS output for data strobe of LVDS bus A. Negative connection. This pin can be left disconnected if not used. H11 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply H12 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply H13 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply H14 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. H15 DCSTR+ O LVDS output for data strobe of LVDS bus C. Positive connection. This pin can be left disconnected if not used. H16 DCSTR– O LVDS output for data strobe of LVDS bus C. Negative connection. This pin can be left disconnected if not used. J1 CLK– I Device (sampling) clock negative input. TI strongly recommends that the clock signal be AC-coupled to this input for best performance. J2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. J3 VA19 I 1.9-V analog supply J4 VA19 I 1.9-V analog supply J5 VA19 I 1.9-V analog supply J6 VA19 I 1.9-V analog supply J7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. J8 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. J9 DBSTR+ O LVDS output for data strobe of LVDS bus B. Positive connection. This pin can be left disconnected if not used. J10 DBSTR– O LVDS output for data strobe of LVDS bus B. Negative connection. This pin can be left disconnected if not used. J11 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply |
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