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TMS465169P Datasheet(PDF) 6 Page - Texas Instruments

Part No. TMS465169P
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS465169P Datasheet(HTML) 6 Page - Texas Instruments

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TMS465169, TMS465169P
HOUSTON, TEXAS 77251–1443
data out (DQ0 – DQ15)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE
are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with
the negative transition of xCAS) as long as tRAC and tAA are satisfied. The delay time from xCAS low to valid
data out is measured from each individual xCAS to its corresponding DQx pin.
output enable (OE)
OE controls the impedance of the output buffers. While xCAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance. There are two methods for placing
the DQs into the high-impedance state and keeping them in that state during xCAS high time by using OE. The
first method is to transition OE high before xCAS transitions high and to keep OE high for tCHO past the xCAS
transition (see Figure 7). This disables the DQs and they remain in the high-impedance state, regardless of OE,
until xCAS falls again. The second method is to have OE low as xCAS transitions high. Then OE can pulse high
for a minimum of tOEP anytime during xCAS high time, disabling the DQs regardless of further transitions on
OE until xCAS falls again (see Figure 7).
RAS-only refresh
A refresh operation must be performed at least once every 64 ms (128 ms for TMS465169P) to retain data. This
is achieved by strobing each of the 4 096 rows for TMS465169 / P. A normal read or write cycle refreshes all bits
in each row that is selected. A RAS-only operation can be used by holding both xCAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pins. This is accomplished by holding
xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle. The external address is ignored and the refresh address is generated internally.
xCAS-before-RAS (xCBR) refresh
An xCBR refresh is achieved by bringing at least one xCAS low earlier than RAS (see parameter tCSR) and
holding it low after RAS falls (see parameter tCHR). For successive xCBR refresh cycles, xCAS can remain low
while cycling RAS. The external address is ignored and the refresh address is generated internally.
battery-backup refresh (TMS465169P)
A low-power battery-backup refresh mode that requires less than 250
µA of refresh current is available on the
TMS465169P. Data integrity is maintained using xCBR refresh with a period of 31.25
µs while holding RAS low
for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels
(VIL < 0.2 V, VIH > VCC – 0.2 V).
self-refresh ( TMS465169P)
The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both
held low for a minimum of 100
µs. The chip is then refreshed internally by an on-board oscillator. No external
address is required because the xCBR counter is used to keep track of the address. To exit the self-refresh
mode, both RAS and xCAS are brought high to satisfy tCHS. Upon exiting self-refresh mode, a burst refresh
(refresh of a full set of row addresses) must be executed before continuing with normal operation. The burst
refresh ensures that the DRAM is completely refreshed.
power up
To achieve proper device operation, an initial pause of 200
µs, followed by a minimum of eight initialization
cycles, is required after power up to the full VCC level. These eight initialization cycles must include at least one
refresh (RAS-only or xCBR) cycle.

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