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MC10EP446FAR2 Datasheet(PDF) 11 Page - ON Semiconductor |
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MC10EP446FAR2 Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 20 page MC10EP446, MC100EP446 http://onsemi.com 11 APPLICATION INFORMATION The MC10/100EP446 is an integrated 8:1 parallel to serial converter. An attribute for EP446 is that the parallel inputs D0–D7 (Pins 17 – 24) can be configured to accept either CMOS, ECL, or TTL level signals by a combination of interconnects between VEF (Pin 27) and VCF (Pin 26) pins. For CMOS input levels, leave VEF and VCF open. For ECL operation, short VCF and VEF (Pins 26 and 27). For TTL operation, connect a 1.5 V supply reference to VCF and leave the VEF pin open. The 1.5 V reference voltage to VCF pin can be accomplished by placing a 1.5 k W or 500 W between VCF and VEE for 3.3 V or 5.0 V power supplies, respectively. Note: all pins requiring ECL voltage inputs must have a 50 W terminating resistor to VTT (VTT = VCC – 2.0 V). The CKSEL input (Pin 2) is provided to enable the user to select the serial data rate output between internal clock data rate or twice the internal clock data rate. For CKSEL LOW operation, the time from when the parallel data is latched ¬ to when the data is seen on the SOUT is on the falling edge of the 7th clock cycle plus internal propagation delay (Figure 6). Note the PCLK switches on the falling edge of CLK. Figure 6. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW CLK SOUT PCLK D0 D0−2 D1 D2 D3 D4 D5 D6 D7 D2−2 D3−2 D4−2 D5−2 D6−2 D7−2 D0−3 D1−3 D2−3 D3−3 D4−3 D5−3 D6−3 D7−3 D1−2 CKSEL D0−1 D2−1 D3−1 D4−1 D5−1 D6−1 D7−1 D1−1 D0−4 D1−4 D2−4 D3−4 D4−4 D5−4 D6−4 D7−4 123 4 567 Number of Clock Cycles from Data Latch to SOUT Data Latched Data Latched Data Latched Data Latched À Á |
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