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MAX1162 Datasheet(PDF) 4 Page - Maxim Integrated Products

Part No. MAX1162
Description  16-Bit, 5V, 200ksps ADC with 10μA Shutdown
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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MAX1162 Datasheet(HTML) 4 Page - Maxim Integrated Products

 
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16-Bit, +5V, 200ksps ADC with 10µA Shutdown
4
_______________________________________________________________________________________
Note 1: AVDD = DVDD = +5V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset and reference errors nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, TA = TMIN
to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Acquisition Time
tACQ
1.1
µs
SCLK to DOUT Valid
tDO
CDOUT = 50pF
50
ns
CS Fall to DOUT Enable
tDV
CDOUT = 50pF
80
ns
CS Rise to DOUT Disable
tTR
CDOUT = 50pF
80
ns
CS Pulse Width
tCSW
50
ns
CS Fall to SCLK Rise Setup
tCSS
100
ns
CS Rise to SCLK Rise Hold
tCSH
0ns
SCLK High Pulse Width
tCH
65
ns
SCLK Low Pulse Width
tCL
65
ns
SCLK Period
tCP
208
ns
TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF =
+4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Acquisition Time
tACQ
1.1
µs
SCLK to DOUT Valid
tDO
CDOUT = 50pF
100
ns
CS Fall to DOUT Enable
tDV
CDOUT = 50pF
100
ns
CS Rise to DOUT Disable
tTR
CDOUT = 50pF
80
ns
CS Pulse Width
tCSW
50
ns
CS Fall to SCLK Rise Setup
tCSS
100
ns
CS Rise to SCLK Rise Hold
tCSH
0ns
SCLK High Pulse Width
tCH
65
ns
SCLK Low Pulse Width
tCL
65
ns
SCLK Period
tCP
208
ns
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = +4.096V, CREF = 4.7µF,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Shutdown Supply Current
IAVDD +
IDVDD
CS = DVDD, SCLK = idle
0.1
10
µA
Power-Supply Rejection Ratio
PSRR
AVDD = DVDD = +4.75V to +5.25V, full-scale
input (Note 5)
68
dB


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