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LTC4251B Datasheet(PDF) 16 Page - Linear Technology

Part No. LTC4251B
Description  Negative Voltage Hot Swap Controllers in SOT-23
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Maker  LINER [Linear Technology]
Homepage  http://www.linear.com
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LTC4251B Datasheet(HTML) 16 Page - Linear Technology

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4251b12f
LTC4251B/LTC4251B-1/
LTC4251B-2
is charged by a 230μA current-source pull-up. At time
point 6, the analog current limit loop activates. Between
time point 6 and time point 7, the GATE voltage is held
essentially constant and the sense voltage is regulated at
VACL. As the load capacitor nears full charge, its current
begins to decline. At point 7, the load current falls and
the sense voltage drops below VACL. The analog current
limit loop shuts off and the GATE pin ramps further. At
time point 8, the sense voltage drops below VCB and
TIMER now discharges through a 5.8μA current source
pull-down. At time point 9, GATE reaches its maximum
voltage as determined by VIN.
Live Insertion with Short Pin Control of UV/OV
In this example as shown in Figure 8, power is delivered
through long connector pins whereas the UV/OV divider
makes contact through a short pin. This ensures the power
connections are firmly established before the LTC4251B/
LTC4251B-1/LTC4251B-2 are activated. At time point 1,
the power pins make contact and VIN ramps through
VLKO. At time point 2, the UV/OV divider makes contact
and its voltage exceeds VUVHI. In addition, the internal
logic checks for VUVHI < UV/OV < VOVHI, TIMER < VTMRL,
GATE < VGATEL and SENSE < VCB. When all conditions are
met, an initial timing cycle starts and the TIMER capaci-
tor is charged by a 5.8μA current source pull-up. At time
point 3, TIMER reaches the VTMRH threshold and the ini-
tial timing cycle terminates. The TIMER capacitor is then
quickly discharged. At time point 4, the VTMRL threshold
is reached and the conditions of GATE < VGATEL and
SENSE < VCB must be satisfied before a start-up cycle is
allowed to begin. GATE sources 58μA into the external
MOSFET gate and compensation network. When the
GATE voltage reaches the MOSFET’s threshold, current
begins flowing into the load capacitor. At time point 5, the
SENSE voltage (VSENSE – VEE ) reaches the VCB threshold
and activates the TIMER. The TIMER capacitor is charged
by a 230μA current source pull-up. At time point 6, the
analog current limit loop activates. Between time point
6 and time point 7, the GATE voltage is held essentially
constant and the sense voltage is regulated at VACL. As
the load capacitor nears full charge, its current begins to
APPLICATIONS INFORMATION
decline. At time point 7, the load current falls and the sense
voltage drops below VACL. The analog current limit loop
shuts off and the GATE pin ramps further. At time point
8, the sense voltage drops below VCB and TIMER now
discharges through a 5.8μA current source pull-down.
At time point 9, GATE reaches its maximum voltage as
determined by VIN.
Undervoltage Lockout Timing
In Figure 9, when UV/OV drops below VUVLO (time point 1),
TIMER and GATE pull low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
When UV/OV recovers and clears VUVHI (time point 2),
an initial time cycle begins followed by a start-up cycle.
Undervoltage Timing with Overvoltage Glitch
In Figure 10, when UV/OV clears VUVHI (time point 1),
an initial timing cycle starts. If the system bus voltage
overshoots VOVHI as shown at time point 2, TIMER dis-
charges. At time point 3, the supply voltage recovers and
drops below the VOVLO threshold. The initial timing cycle
restarts followed by a start-up cycle.
Overvoltage Timing
During normal operation, if UV/OV exceeds VOVHI as
shown at time point 1 of Figure 11, the TIMER status is
unaffected. Nevertheless, GATE pulls down and discon-
nects the load. At time point 2, UV/OV recovers and drops
below the VOVLO threshold. A gate ramp up cycle ensues.
If the overvoltage glitch is long enough to deplete the
load capacitor, a full start-up cycle may occur as shown
between time points 3 through 6.
Timer Behavior
In Figure 12a, the TIMER capacitor charges at 230μA if
the SENSE pin exceeds VCB. It is discharged with 5.8μA
if the SENSE pin is less than VCB. In Figure 12b, when
TIMER exceeds VTMRH, TIMER is latched high by the 5.8μA
pull-up and GATE pulls down immediately. In Figure 12c,
multiple momentary faults cause the TIMER capacitor to
integrate until it latches.


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