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LTC1858 Datasheet(PDF) 33 Page - Linear Technology |
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LTC1858 Datasheet(HTML) 33 Page - Linear Technology |
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33 / 40 page  LTC2345-16 33 234516f For more information www.linear.com/LTC2345-16 SCKO frequency is half that of SCKI. SCKI rising edges alsolatchSoftSpanconfigurationwordsprovidedonSDI, which are used to program the internal 24-bit SoftSpan configuration register. See the section Programming the SoftSpan Configuration Register in CMOS I/O Mode for further details. SCKI is allowed to idle either high or low in CMOS I/O mode. As shown in Figure 18, the CMOS bus is enabled when CS is low and is disabled and Hi-Z when CS is high, allowing the bus to be shared across multiple devices. The data on SDO0 to SDO7 are grouped into 24-bit packets consisting of a 16-bit conversion result plus 2-bit trailing zero pad, 3-bit analog channel ID, and 3-bit SoftSpan code, all presented MSB first. As suggested in Figures 17 and 18, each SDO lane outputs these packets for all analog input channels in a sequential, circular manner. For example, the first 24-bit packet output on SDO0 corresponds to analog input channel 0, followed by the packets for channels 1 through 7. The data output on SDO0 then wraps back to channel 0, and this pattern repeats indefinitely. Other SDO lanes follow a similar circular pattern, except the first packet presented on each lane corresponds to its associated analog input channel. When interfacing the LTC2345-16 with a standard SPI bus, capture output data at the receiver on rising edges of SCKI. SCKO is not used in this case. Multiple SDO lanes are also usually not useful in this case. In other applica- tions, such as interfacing the LTC2345-16 with an FPGA or CPLD, rising and falling edges of SCKO may be used to capture serial output data on SDO0 to SDO7 in double data rate (DDR) fashion. Capturing data using SCKO adds robustnesstodelayvariationsovertemperatureandsupply. Full Eight Lane Serial CMOS Output Data Capture As shown in Table 3, full 200ksps per channel throughput canbeachievedwitha45MHzSCKIfrequencybycapturing the first packet (24 SCKI cycles total) from all eight serial data output lanes SDO0 to SDO7. This configuration also allows conversion results from all channels to be captured using as few as 16 SCKI cycles if the 3-bit analog channel ID and 3-bit SoftSpan code are not needed and the device SoftSpan configuration is not being changed. Multi-lane data capture is usually best suited for use with FPGA or CPLD capture hardware, but may be useful in other application-specific cases. Fewer Than Eight Lane Serial CMOS Output Data Capture Applications that cannot accommodate the full eight lanes of serial data capture may employ fewer lanes without reconfiguring the LTC2345-16. For example, capturing the first two packets (48 SCKI cycles total) from SDO0, SDO2, SDO4, and SDO6 provides data for analog input applicaTions inForMaTion CS PD = 0 DON’T CARE BUSY SDO7 SCKO SDO0 SCKI SDI DON’T CARE DON’T CARE DON’T CARE 234516 F18 Hi-Z Hi-Z CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 2 PACKET CHANNEL 3 PACKET (PARTIAL) Hi-Z Hi-Z Hi-Z Hi-Z CHANNEL 7 PACKET CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 2 PACKET (PARTIAL) NEW SoftSpan CONFIGURATION WORD (OVERWRITES INTERNAL CONFIG REGISTER) TWO ALL-ZERO WORDS AND ONE PARTIAL WORD (INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE) tEN tDIS Figure 18. Internal SoftSpan Configuration Register Behavior. Serial CMOS Bus Response to CS |
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