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LTC2380-16 Datasheet(PDF) 8 Page - Linear Technology

Part # LTC2380-16
Description  Dual, 16-Bit, 5Msps Differential Input ADC with Wide Input Common Mode Range
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2380-16 Datasheet(HTML) 8 Page - Linear Technology

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LTC2323-16
8
232316fc
For more information www.linear.com/LTC2323-16
PIN FUNCTIONS
VDD (Pins 1, 8): Power Supply. Bypass VDD to GND with
a 10µF ceramic and a 0.1µF ceramic close to the part. The
VDD pins should be shorted together and driven from the
same supply.
AIN2+, AIN2– (Pins 2, 3): Analog Differential Input Pins.
Full-scale range (AIN2+ – AIN2–) is ±REFOUT2 voltage.
These pins can be driven from VDD to GND.
GND (Pins 4, 5, 10, 29): Ground. These pins and exposed
pad (Pin 29) must be tied directly to a solid ground plane.
AIN1–, AIN1+ (Pins 6, 7): Analog Differential Input Pins.
Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage.
These pins can be driven from VDD to GND.
CNV (Pin 9): Conversion Start Input. A falling edge on CNV
puts the internal sample-and-hold into the hold mode and
starts a conversion cycle. CNV must be driven by a low
jitter clock as shown in the application circuit on page 26.
The CNV pin is unaffected by the CMOS/LVDS pin.
REFRTN1 (Pin 11): Reference Buffer 1 Output Return.
Bypass REFRTN1 to REFOUT1. Do not tie the REFRTN1
pin to the ground plane.
REFOUT1 (Pin 12): Reference Buffer 1 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to REFRTN1 and should be decoupled closely to
the pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor
and a 10μF (X5R, 0805 size) ceramic capacitor in paral-
lel. The internal buffer driving this pin may be disabled
by grounding the REFINT pin. If the buffer is disabled,
an external reference may drive this pin in the range of
1.25V to 5V.
VBYP1 (Pin 13): Bypass this internally supplied pin to
ground with a 1µF ceramic capacitor. The nominal output
voltage on this pin is 1.6V.
OVDD (Pin 14): I/O Interface Digital Power. The range of
OVDD is 1.71V to 2.5V. This supply is nominally set to
the same supply as the host interface (CMOS: 1.8V or
2.5V, LVDS: 2.5V). Bypass OVDD to OGND with a 0.1μF
capacitor.
SDO1+, SDO1(Pins 15, 16): Channel 1 Serial Data
Output. The conversion result is shifted MSB first on each
falling edge of SCK. In CMOS mode, the result is output
on SDO1+. The logic level is determined by OVDD. Do
not connect SDO1. In LVDS mode, the result is output
differentially on SDO1+ and SDO1. These pins must be
differentially terminated by an external 100Ω resistor at
the receiver (FPGA).
CLKOUT+, CLKOUT(Pins 17, 18): Serial Data Clock
Output. CLKOUT provides a skew-matched clock to latch
the SDO output at the receiver. In CMOS mode, the skew-
matched clock is output on CLKOUT+. The logic level is
determined by OVDD. Do not connect CLKOUT. For low
throughput applications using SCK to latch the SDO out-
put, CLKOUT+ can be disabled by tying CLKOUTto OVDD.
In LVDS mode, the skew-matched clock is output differ-
entially on CLKOUT+ and CLKOUT. These pins must be
differentially terminated by an external 100Ω resistor at
the receiver (FPGA).
SDO2+, SDO2(Pins 19, 20): Channel 2 Serial Data
Output. The conversion result is shifted MSB first on each
falling edge of SCK. In CMOS mode, the result is output
on SDO2+. The logic level is determined by OVDD. Do
not connect SDO2. In LVDS mode, the result is output
differentially on SDO2+ and SDO2. These pins must be
differentially terminated by an external 100Ω resistor at
the receiver (FPGA).
SCK+, SCK(Pins 21, 22): Serial Data Clock Input. The
falling edge of this clock shifts the conversion result MSB
first onto the SDO pins. In CMOS mode, drive SCK+ with
a single-ended clock. The logic level is determined by
OVDD. Do not connect SCK. In LVDS mode, drive SCK+
and SCKwith a differential clock. These pins must be
differentially terminated by an external 100Ω resistor at
the receiver (ADC).
OGND (Pin 23): I/O Ground. This ground must be tied to
the ground plane at a single point. OVDD is bypassed to
this pin.


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